74vhc132mx-nl Fairchild Semiconductor, 74vhc132mx-nl Datasheet

74vhc132mx-nl

Manufacturer Part Number

74vhc132mx-nl

Description

74vhc132 Quad 2-input Nand Schmitt Trigger

Manufacturer

Fairchild Semiconductor

Datasheet

1.74VHC132MX-NL.pdf (9 pages)

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74VHC132 Rev. 1.4

74VHC132

Quad 2-Input NAND Schmitt Trigger

Features

■

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number. Pb-Free package per JEDEC J-STD-020B.

Note:

1. Device available in Tape and Reel only.

74VHC132M

74VHC132MX_NL

74VHC132SJ

74VHC132MTC

74VHC132MTCX_NL

High Speed: t

Power down protection is provided on all inputs

Low power dissipation: I

Low noise: V

Pin and function compatible with 74HC132

Order Number

OLP

= 3.9ns (Typ.) at V

(1)

= 0.8V (Max.)

(1)

Package

Number

= 2µA (Max.) at T

MTC14

M14A

M14D

= 5V

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

= 25°C

General Description

The VHC132 is an advanced high speed CMOS 2-input

NAND Schmitt Trigger Gate fabricated with silicon gate

CMOS technology. It achieves the high-speed operation

similar to Bipolar Schottky TTL while maintaining the

CMOS low power dissipation. Pin configuration and

function are the same as the VHC00 but the inputs have

hysteresis between the positive-going and negative-

going input thresholds, which are capable of transform-

ing slowly changing input signals into sharply defined,

jitter-free output signals. Thus greater noise margin then

conventional gates is provided. An input protection

circuit ensures that 0V to 7V can be applied to the input

pins without regard to the supply voltage. This device

can be used to interface 5V to 3V systems and two

supply systems such as battery backup. This circuit

prevents device destruction due to mismatched supply

and input voltages.

Package Description

www.fairchildsemi.com

May 2007

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