74vhc161mx-nl Fairchild Semiconductor, 74vhc161mx-nl Datasheet
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74vhc161mx-nl
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74vhc161mx-nl Summary of contents
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... M16D 74VHC161MTC MTC16 Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Connection Diagram ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 General Description = 25°C The VHC161 is an advanced high-speed CMOS device A fabricated with silicon gate CMOS technology. It ...
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... Five control inputs—Master Reset, Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle Figure 2. Multistage Counter with Lookahead Carry ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 (CET)—determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW ...
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... No Change (Hold HIGH Voltage Level L = LOW Voltage Level X = Immaterial Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 State Diagram Clock Edge ( ) → ...
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... Operating Temperature OPR Input Rise and Fall Time 3.3V ± 0. 5.0V ± 0. Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 Parameter (1) Parameter 4 Rating –0.5V to +7.0V –0.5V to +7.0V –0. 0.5V CC –20mA ±20mA ±25mA ± ...
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... Quiet Output Minimum OLV Dynamic V OL (2) V Minimum HIGH Level IHD Dynamic Input Voltage (2) V Maximum LOW Level ILD Dynamic Input Voltage Note: 2. Parameter guaranteed by design. ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 (V) Conditions Min. 1.50 0 –50µ 1 ...
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... When the outputs drive a capacitive load, total current consumption is the sum of C from the following formula: C –C and C are the capacitances at Q0–Q3 and TC, respectively ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 V (V) Conditions CC = 15pF 3.3 ± 0 50pF 15pF 5.0 ± ...
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... Minimum Hold Time (PE –CP Minimum Hold Time (CEP or CET–CP (L), t (H) Minimum Pulse Width CP (Count (L) Minimum Pulse Width (MR Minimum Removal Time REC Note 3.3 ± 0.3V or 5.0 ± 0.5V. CC ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 (4) V (V) Typ. CC –CP) 3.3 n 5.0 3.3 5.0 3.3 5.0 –CP) 3.3 n 5.0 3.3 5.0 3 ...
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... Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 3. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 Package Number M16A 8 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 4. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 Package Number M16D 9 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. 5.00±0.10 4.55 0.11 MTC16rev4 Figure 5. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 0.65 4.4±0.1 1.45 Package Number MTC16 10 5.90 4.45 7.35 5.00 12° www.fairchildsemi.com ...
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... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ ...