hef4520b NXP Semiconductors, hef4520b Datasheet - Page 2

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hef4520b

Manufacturer Part Number
hef4520b
Description
Dual Binary Counter
Manufacturer
NXP Semiconductors
Datasheet

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DESCRIPTION
The HEF4520B is a dual 4-bit internally synchronous
binary counter. The counter has an active HIGH clock
input (CP
outputs from all four bit positions (O
HIGH overriding asynchronous master reset input (MR).
The counter advances on either the LOW to HIGH
transition of the CP
PINNING
FAMILY DATA, I
See Family Specifications
January 1995
CP
CP
MR
O
O
Dual binary counter
0A
0B
0A
1A
A
to O
to O
, MR
, CP
, CP
0
3A
3B
) and an active LOW clock input (CP
B
0B
1B
Fig.1 Functional diagram.
DD
clock inputs (L to H triggered)
clock inputs (H to L triggered)
master reset inputs
outputs
outputs
0
LIMITS category MSI
input if CP
1
is HIGH or the HIGH to
0
to O
3
) and an active
1
), buffered
2
LOW transition of the CP
CP
other clock input may be used as a clock enable input. A
HIGH on MR resets the counter (O
independent of CP
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
HEF4520BP(N):
HEF4520BD(F):
HEF4520BT(D):
( ): Package Designator North America
1
may be used as the clock input to the counter and the
Fig.2 Pinning diagram.
0
, CP
16-lead DIL; plastic
16-lead DIL; ceramic (cerdip)
16-lead SO; plastic (SOT109-1)
(SOT38-1)
(SOT74)
(SOT109-1)
1
1
.
input if CP
Product specification
0
0
to O
is low. Either CP
HEF4520B
3
= LOW)
MSI
0
or

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