74hct193 NXP Semiconductors, 74hct193 Datasheet

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74hct193

Manufacturer Part Number
74hct193
Description
Presettable Synchronous 4-bit Binary Up/down Counter
Manufacturer
NXP Semiconductors
Datasheet

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74hct193D
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20 000
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74hct193D652
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NXP Semiconductors
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1. General description
The 74HC193 and 74HCT193 are high-speed Si-gate CMOS devices and are pin
compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC193 and 74HCT193 are 4-bit synchronous binary up/down counters. Separate
up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state
synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is
pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while
CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at
any time, or erroneous operation will result. The device can be cleared at any time by the
asynchronous master reset input (MR); it may also be loaded in parallel by activating the
asynchronous parallel load input (PL).
The 74HC193 and 74HCT193 each contain four master-slave JK flip-flops with the
necessary steering logic to provide the asynchronous reset, load, and synchronous count
up and count down functions.
Each flip-flop contains JK feedback from slave to master, such that a LOW-to-HIGH
transition on the CPD input will decrease the count by one, while a similar transition on the
CPU input will advance the count by one.
One clock should be held HIGH while counting with the other, otherwise the circuit will
either count by twos or not at all, depending on the state of the first flip-flop, which cannot
toggle as long as either clock input is LOW. Applications requiring reversible operation
must make the reversing decision while the activating clock is HIGH to avoid erroneous
counts.
The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH.
When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW
transition of CPU will cause TCU to go LOW.
TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock.
Likewise, the TCD output will go LOW when the circuit is in the zero state and the
CPD goes LOW. The terminal count outputs can be used as the clock input signals to the
next higher order circuit in a multistage counter, since they duplicate the clock waveforms.
Multistage counters will not be fully synchronous, since there is a slight delay time
difference added for each stage that is added.
The counter may be preset by the asynchronous parallel load capability of the circuit.
Information present on the parallel data inputs (D0 to D3) is loaded into the counter and
appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when
the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will
disable the parallel load gates, override both clock inputs and set all outputs (Q0 to
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Rev. 03 — 23 May 2007
Product data sheet

Related parts for 74hct193

74hct193 Summary of contents

Page 1

... The 74HC193 and 74HCT193 each contain four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, load, and synchronous count up and count down functions. ...

Page 2

... TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4 TCU 12 TCD 001aag405 Fig 2. Logic symbol Rev. 03 — 23 May 2007 74HC193; 74HCT193 CPU 5 12 CPD 4 13 ...

Page 3

... NXP Semiconductors Fig 3. IEC logic symbol 74HC_HCT193_3 Product data sheet 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter CTR4 2CT = 0 12 1CT = 15 001aag410 Rev. 03 — 23 May 2007 © NXP B.V. 2007. All rights reserved. ...

Page 4

D0 PL CPU FF1 Q RD CPD MR Q0 Fig 4. Logic diagram FF2 T FF3 TCU FF4 Q RD ...

Page 5

... CPD 4 CPU 5 GND TCU 12 TCD [1] LOW-to-HIGH, edge triggered. 74HC_HCT193_3 Product data sheet 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter 74HC193 74HCT193 CPD 4 13 CPU GND ...

Page 6

... Rev. 03 — 23 May 2007 74HC193; 74HCT193 Outputs ...

Page 7

... Fig 8. Typical clear, load and count sequence 74HC_HCT193_3 Product data sheet 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter ...

Page 8

... SSOP16 package TSSOP16 package derates linearly at 12 mW/K. tot derates linearly at 8 mW/K. tot derates linearly at 5.5 mW/K. tot Conditions inputs inputs Rev. 03 — 23 May 2007 74HC193; 74HCT193 Min Max 0.5 +7 +150 [2] - 750 [2] - 500 [2] - 500 [2] - ...

Page 9

... 6 4 5 GND 6 GND Rev. 03 — 23 May 2007 74HC193; 74HCT193 Min Typ 4.5 5 +25 - 6.0 - 6.0 Min Typ Max 1.5 1.2 - 3.15 2.4 - 4.2 3 0.8 0.5 - 2.1 1.35 - 2.8 1 1.9 2 ...

Page 10

... 6 4 5 GND 6 GND 6 Rev. 03 — 23 May 2007 74HC193; 74HCT193 Min Typ Max - - 0 1. 1 ...

Page 11

... NXP Semiconductors Table 7. Static characteristics type 74HCT193 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I supply current ...

Page 12

... NXP Semiconductors Table 7. Static characteristics type 74HCT193 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I supply current CC I additional supply current CC 74HC_HCT193_3 Product data sheet Presettable synchronous 4-bit binary up/down counter … ...

Page 13

... Figure Figure Rev. 03 — 23 May 2007 74HC193; 74HCT193 + +125 C Unit Max Min Max Min 215 - 270 - 125 - 155 - 125 - 155 ...

Page 14

... Figure Figure Rev. 03 — 23 May 2007 74HC193; 74HCT193 + +125 C Unit Max Min Max Min 290 - 365 - ...

Page 15

... 2.0 V 4 where Rev. 03 — 23 May 2007 74HC193; 74HCT193 + +125 C Unit Max Min Max Min - 100 - 120 - 100 - 120 ...

Page 16

... NXP Semiconductors Table 9. Dynamic characteristics type 74HCT193 Symbol Parameter Conditions t propagation CPU, CPD to Qn; pd delay see V CPU to TCU; see Figure 10 V CPD to TCD; see Figure Qn; see Figure Qn; see Figure Qn; see Figure TCU TCD ...

Page 17

... NXP Semiconductors Table 9. Dynamic characteristics type 74HCT193 Symbol Parameter Conditions t recovery time PL to CPU, CPD; rec see CPU, CPD; see V t set-up time Dn to PL; see su Figure CPU = CPD = HIGH V t hold time Dn to PL; see h Figure 13 V CPU to CPD, CPD to CPU; see ...

Page 18

... CPU, CPD V M input GND PHL output Table 10 input GND t PHL output V OL Table 10 Rev. 03 — 23 May 2007 74HC193; 74HCT193 t PLH 001aag413 t PLH 001aag414 © NXP B.V. 2007. All rights reserved ...

Page 19

... input V M GND rec V I CPU, CPD input GND t PHL output THL Table 10 Rev. 03 — 23 May 2007 74HC193; 74HCT193 t rec PHL 001aag415 TLH 001aag416 © NXP B.V. 2007. All rights reserved ...

Page 20

... V OH TCU, TCD V M output V OL Table 10 CPU or CPD input GND CPD or CPU V M input GND Table 10. Rev. 03 — 23 May 2007 74HC193; 74HCT193 001aag417 t PHL 001aag418 V M 001aag419 © NXP B.V. 2007. All rights reserved ...

Page 21

... V M pulse DUT R T Load pF pF Rev. 03 — 23 May 2007 74HC193; 74HCT193 Output open C L 001aad983 of the pulse generator ...

Page 22

... clock CPU TCU IC1 down clock CPD TCD reset data output Rev. 03 — 23 May 2007 74HC193; 74HCT193 CPU TCU carry IC2 CPD TCD borrow 001aag420 © NXP B.V. 2007. All rights reserved. ...

Page 23

... 0.49 0.25 10.0 4.0 1.27 0.36 0.19 9.8 3.8 0.019 0.0100 0.39 0.16 0.244 0.05 0.014 0.0075 0.38 0.15 0.228 REFERENCES JEDEC JEITA MS-012 Rev. 03 — 23 May 2007 74HC193; 74HCT193 detail 6.2 1.0 0.7 1.05 0.25 0.25 5.8 0.4 0.6 0.039 0.028 0.041 0.01 0.01 ...

Page 24

... Presettable synchronous 4-bit binary up/down counter 2.5 scale (1) ( 0.38 0.20 6.4 5.4 7.9 0.65 0.25 0.09 6.0 5.2 7.6 REFERENCES JEDEC JEITA MO-150 Rev. 03 — 23 May 2007 74HC193; 74HCT193 detail 1.03 0.9 0.2 0.13 1.25 0.63 0.7 EUROPEAN PROJECTION SOT338 ...

Page 25

... Presettable synchronous 4-bit binary up/down counter scale ( 1.73 0.53 1.25 0.36 19.50 1.30 0.38 0.85 0.23 18.55 0.068 0.021 0.049 0.014 0.77 0.051 0.015 0.033 0.009 0.73 REFERENCES JEDEC JEITA Rev. 03 — 23 May 2007 74HC193; 74HCT193 ( 6.48 3.60 8.25 2.54 7.62 6.20 3.05 7.80 0.26 0.14 0.32 0.1 0.3 0.24 0.12 0.31 ...

Page 26

... Presettable synchronous 4-bit binary up/down counter 2.5 scale (1) ( 0.30 0.2 5.1 4.5 0.65 0.19 0.1 4.9 4.3 REFERENCES JEDEC JEITA MO-153 Rev. 03 — 23 May 2007 74HC193; 74HCT193 detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN ...

Page 27

... Legal texts have been adapted to the new company name where appropriate. • Family specification included 74HC_HCT193_CNV_2 19970828 74HC_HCT193_3 Product data sheet 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Data sheet status Change notice Product data sheet - Product specification - Rev. 03 — ...

Page 28

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 23 May 2007 74HC193; 74HCT193 © NXP B.V. 2007. All rights reserved ...

Page 29

... Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 17 Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...

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