nbsg53a ON Semiconductor, nbsg53a Datasheet - Page 9

• Manufacturer Part Number: nbsg53a
• Description: 2.5v/3.3v Sige Selectable Differential Clock And Data D Flip-flop/clock Divider With Reset And Ols
• Manufacturer: ON Semiconductor

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
26. Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50 W to
27. See Figure 14. t
28. V
29. See Figure 10. Duty Cycle % vs. Frequency.
**When an output level of 400 mV is desired and V
Table 10. AC CHARACTERISTICS for FCBGA−16
V
Symbol
f
t
t
t
t
V
t
t
t
t
t
max
PLH
PHL
SKEW
JITTER
r
f
s
h
rr
CC
INPP
V
CC
INPP
,
= 0 V; V
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
− 2.0 V. Input edge rates is 40 ps (20% − 80%).
(MAX) cannot exceed V
Maximum Frequency
(See Figures 4, 6, 8, 10, and 11)
(See Figures 5, 7, 9, 10, and 11)
(Note 26)
Propagation Delay to Output Differential
Duty Cycle Skew (Notes 27 and 29) DFF
RMS Random Clock Jitter
(See Figures 4 and 6) (Note 26)
Peak−to−Peak Data Dependent Jitter
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 28)
Output Rise/Fall Times (20% − 80%)
@ 1 GHz
Setup Time
Hold Time
Reset Recovery
(OLS = V
EE
(OLS = V
= −3.465 V to −2.375 V or V
(OLS = V
(OLS = V
(OLS = V
SKEW
CC
CC
−0.8 V, OLS = FLOAT) DIV/2
= |t
Characteristic
− 0.8 V, OLS = FLOAT) DFF
(OLS = V
CC
CC
CC
PLH
(OLS = V
− 0.8 V, OLS = FLOAT)
− 0.8 V, OLS = FLOAT)
− 0.8 V, OLS = FLOAT)
− t
CC
(OLS = V
(OLS = V
**(OLS = V
(OLS = V
**(OLS = V
(OLS = V
PHL
(OLS = V
CC
− V
CC
| for a nominal 50% differential clock input waveform.
**(OLS = V
**(OLS = V
**(OLS = V
− 0.4 V) DIV/2
EE
− 0.4 V) DFF
(OLS = V
(OLS = V
(OLS = V
f
CLK→Q, Q
in
f
CC
SEL→Q, Q
CC
CC
DFF, DIV/2
(Applicable only when V
in
CC
EE
v 8 GHz
R→Q, Q
= 8 Gb/s
CC
CC
EE
D→CLK
D→CLK
− 0.4 V)
− 0.4 V)
− 0.4 V)
) DIV/2
) DIV/2
) DFF
) DFF
DIV/2
= 2.375 V to 3.465 V; V
Q, Q
DFF
CC
CC
CC
CC
EE
EE
EE
)
)
)
)
)
)
− V
Min
160
150
155
155
165
160
160
160
220
200
215
195
220
200
215
195
EE
75
30
20
25
25
30
25
40
http://onsemi.com
> 3.0 V, a 2 kW resistor should be connected from OLS to V
−40°C
Typ
210
200
205
205
220
210
215
210
295
270
285
260
290
265
285
260
0.5
10
50
40
45
45
14
12
8
5
9
CC
9
− V
EE
2600
Max
260
250
255
255
275
260
270
260
370
340
355
325
360
330
355
325
EE
1.5
20
65
60
65
65
= 0 V
< 2600 mV).
Min
160
155
160
160
170
160
165
160
225
205
220
200
220
200
220
200
75
30
20
25
25
30
25
40
25°C
TBD
Typ
215
205
210
210
225
210
220
215
300
275
290
265
295
270
290
265
0.5
10
50
40
45
45
10
12
8
5
7
2600
Max
270
255
260
260
280
260
275
270
375
345
360
330
370
340
360
330
1.5
20
65
60
65
65
Min
165
160
160
160
170
160
165
165
225
205
220
200
220
200
220
200
75
30
20
25
25
30
25
40
70°C
Typ
220
210
215
215
225
210
220
220
300
275
290
265
295
270
290
265
0.5
10
50
40
45
45
13
10
8
5
9
EE
.
2600
Max
275
260
270
270
280
260
275
275
375
345
360
330
370
340
360
330
1.5
20
65
60
65
65
GHz
Unit
mV
ps
ps
ps
ps
ps
ps
ps