nb7l14 ON Semiconductor, nb7l14 Datasheet - Page 2

• Manufacturer Part Number: nb7l14
• Description: 2.5v / 3.3v 7ghz/10gbps Differential 1 4 Lvpecl Fanout Buffer
• Manufacturer: ON Semiconductor

1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
Table 1. PIN DESCRIPTION
Pin
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
−
is applied on IN/IN input, then, the device will be susceptible to self−oscillation.
VREFAC
Name
GND
GND
VCC
VCC
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
EP
VT
IN
IN
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVDS, LVTTL
LVDS, LVTTL
ECL, CML,
ECL, CML,
LVCMOS,
LVCMOS,
Input
Input
I/O
−
−
−
−
−
−
V
REFAC
Non−inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VT
Internal 50−W Termination Pin for IN/IN inputs.
Output Reference Voltage for capacitor−coupled inputs
Inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VT.
Negative Supply Voltage
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V
Positive Supply Voltage
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V
Positive Supply Voltage
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V
Negative Supply Voltage
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is not electrically connected to the die, but is recommended to be electrically
and thermally connected to GND on the PC board.
VT
IN
IN
Figure 2. QFN−16 Pinout (Top View)
1
2
3
4
GND
GND Q0
16
5
http://onsemi.com
15
Q3
NB7L14
6
Q0
14
Q3
2
7
V
V
13
8
CC
CC
Exposed Pad (EP)
Description
12
11
10
9
Q1
Q1
Q2
Q2
CC
CC
CC
CC
– 2.0 V.
– 2.0 V.
– 2.0 V.
– 2.0 V.
CC
CC
CC
CC
– 2.0 V.
– 2.0 V.
– 2.0 V.
– 2.0 V.