nb7l14 ON Semiconductor, nb7l14 Datasheet

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nb7l14

Manufacturer Part Number
nb7l14
Description
2.5v / 3.3v 7ghz/10gbps Differential 1 4 Lvpecl Fanout Buffer
Manufacturer
ON Semiconductor
Datasheet

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NB7L14
2.5V / 3.3V 7GHz/10Gbps
Differential 1:4 LVPECL
Fanout Buffer
Multi−Level Inputs w/ Internal
Termination
Description
NB7L14 produces four identical LVPECL output copies of Clock or
Data operating up to 7 GHz or 10.7 Gb/s, respectively. As such, the
NB7L14 is ideal for SONET, GigE, Fiber Channel, Backplane and
other Clock or Data distribution applications.
resistors that are accessed through the VT Pin. This feature allows the
NB7L14 to accept various logic standards, such as LVPECL, CML,
LVDS, LVCMOS or LVTTL logic levels. The V
output can be used to rebias capacitor−coupled differential or
single−ended input signals. The 1:4 fanout design was optimized for
low output skew applications.
performance clock products.
Features
© Semiconductor Components Industries, LLC, 2008
September, 2008 − Rev. 0
The NB7L14 is a differential 1:4 LVPECL fanout buffer. The
The differential inputs incorporate internal 50 W termination
The NB7L14 is a member of the GigaComm™ family of high
EP, and SG Devices
Input Data Rate > 10.7 Gb/s
Input Clock Frequency > 7 GHz
165 ps Typical Propagation Delay
45 ps Typical Rise and Fall Times
<15 ps max Output Skew
<0.8 ps maximum RMS Clock Jitter
<15 ps pp of Data Dependent Jitter
Differential LVPECL Outputs, 720 mV peak−to−peak, typical
LVPECL Operating Range: V
NECL Operating Range: V
Internal Input Termination Resistors, 50 W
V
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
REFAC
Reference Output
CC
CC
= 0 V with GND = −2.375 V to −3.6 V
= 2.375 V to 3.6 V with GND = 0 V
REFAC
reference
1
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
V
VT
50 W
50 W
IN
IN
REFAC
*For additional marking information, refer to
MN SUFFIX
CASE 485G
(Note: Microdot may be in either location)
Application Note AND8002/D.
QFN−16
1
XXXX = Specific Device Code
A
L
Y
W
G
ORDERING INFORMATION
Figure 1. Logic Diagram
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
1
Ç Ç Ç Ç
DIAGRAM*
16
MARKING
ALYWG
NB7L
14
G
NB7L14MD
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3

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nb7l14 Summary of contents

Page 1

... LVDS, LVCMOS or LVTTL logic levels. The V output can be used to rebias capacitor−coupled differential or single−ended input signals. The 1:4 fanout design was optimized for low output skew applications. The NB7L14 is a member of the GigaComm™ family of high performance clock products. Features • ...

Page 2

... IN/IN input, then, the device will be susceptible to self−oscillation. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. GND Exposed Pad (EP NB7L14 GND Figure 2. QFN−16 Pinout (Top View) Description http://onsemi ...

Page 3

Table 2. ATTRIBUTES ESD Protection Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Power Supply ...

Page 4

Table 4. DC CHARACTERISTICS, MULTI−LEVEL INPUTS Symbol Characteristic POWER SUPPLY CURRENT V Power Supply Voltage CC I Power Supply Current (Inputs and Outputs Open) CC LVPECL OUTPUTS (Notes 5 & Output HIGH Voltage OH V Output LOW Voltage ...

Page 5

Table 5. AC CHARACTERISTICS V Symbol f Maximum Input Clock Frequency; V MAX f Maximum Operating Data Rate; NRZ, (PRBS23) DATAMAX V Output Voltage Amplitude (Note 15) OUTPP (See Figure Propagation Delay PLH t ...

Page 6

Figure 5. Differential Input Driven Single−Ended IHmax V thmax V ILmax IHmin V thmin V ILmin GND Figure ...

Page 7

... Connected to External REFAC bypassed to ground with a 0.01 mF capacitor http://onsemi.com NB7L14 Open GND Figure 12. LVDS Interface V CC NB7L14 REFAC GND Differential Interface ) REFAC ...

Page 8

... Figure 16. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device NB7L14MNG NB7L14MNTXG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ ...

Page 9

... MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.18 0.30 D 3.00 BSC D2 1.65 1.85 E 3.00 BSC E2 1.65 1.85 e 0.50 BSC K 0.18 TYP L 0.30 0.50 L1 0.00 0.15 SOLDERING FOOTPRINT* 3.25 0.128 0.30 EXPOSED PAD 0.012 1.50 0.059 0.30 0.012 0.50 0.02 mm SCALE 10:1 inches ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB7L14/D ...

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