max9324eupt Maxim Integrated Products, Inc., max9324eupt Datasheet - Page 7

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max9324eupt

Manufacturer Part Number
max9324eupt
Description
Max9324 One-to-five Lvpecl/lvcmos Output Clock And Data Driver
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
Figure 2. MAX9324 CLK_EN Timing Diagram
SEOUT_Z enables/disables the single-ended LVCMOS
output
the single-ended output. Connect SEOUT_Z to V
force the single-ended output to a high-impedance
state. SEOUT provides a single-ended monitor for oper-
ating frequencies as high as 200MHz.
Table 1. Control Input Table
CLK_EN
SEOUT_Z
One-to-Five LVPECL/LVCMOS Output Clock and
CLK_EN
SEOUT
CLK
CLK
0
0
1
1
Q_
Q_
(Table 1). Connect SEOUT_Z to GND to enable
INPUTS
SEOUT_Z
0
1
0
1
_______________________________________________________________________________________
DISABLED
Disabled, pulled to logic low
Disabled, pulled to logic low
Enabled
Enabled
Q0–Q3
SEOUT_Z
CC
to
Disabled, pulled to logic high
Disabled, pulled to logic high
Terminate both outputs of each differential pair through
50Ω to (V
nation. Use identical termination on each output for the
lowest output-to-output skew. Terminate both outputs
when deriving a single-ended signal from a differential
output. For example, using Q0 as a single-ended out-
put requires termination for both Q0 and Q0.
ENABLED
OUTPUTS
Enabled
Enabled
Q Q Q Q 0 0 0 0 –Q Q Q Q 3 3 3 3
CC
- 2V) or use an equivalent Thevenin termi-
Applications Information
Data Driver
IMPEDANCE
Disabled, high impedance
Disabled, high impedance
Output Termination
HIGH
Enabled, logic low
Enabled
SEOUT
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