max9324eupt Maxim Integrated Products, Inc., max9324eupt Datasheet
max9324eupt
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max9324eupt Summary of contents
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Rev 0; 10/02 One-to-Five LVPECL/LVCMOS Output Clock and General Description The MAX9324 low-skew, low-jitter, clock and data driver distributes a differential LVPECL input to four differential LVPECL outputs and one single-ended LVCMOS output. All outputs default to logic low ...
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver ABSOLUTE MAXIMUM RATINGS V to GND ...........................................................-0.3V to +4.0V CC Q_, Q_, CLK, CLK, SEOUT_Z, CLK_EN, SEOUT to GND.......................................-0. CLK to CLK ............................................................................±3V SEOUT Short to GND .................................................Continuous Continuous Output Current ...
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One-to-Five LVPECL/LVCMOS Output Clock and AC ELECTRICAL CHARACTERISTICS (V = 3.0V to 3.6V, differential outputs terminated with 50Ω ± tion time = 125ps (20% to 80%), V IHD SEOUT_Z = GND -40°C to +85°C, unless ...
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver (V = 3.3V, outputs terminated SUPPLY CURRENT vs. TEMPERATURE 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 -40 -15 10 TEMPERATURE (°C) DIFFERENTIAL OUTPUT RISE/FALL TIME vs. TEMPERATURE ...
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One-to-Five LVPECL/LVCMOS Output Clock and PIN NAME TSSOP QFN GND Ground. Provide a low-impedance connection to the ground plane. Synchronous Output Enable. Connect CLK_EN to V differential outputs. Connect CLK_EN to GND to disable the differential ...
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver Detailed Description The MAX9324 low-skew, low-jitter, clock and data dri- ver distributes a differential LVPECL input signal to four differential LVPECL outputs and a single-ended LVC- MOS output. The differential output drivers operate ...
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One-to-Five LVPECL/LVCMOS Output Clock and CLK CLK DISABLED CLK_EN Q_ Q_ SEOUT SEOUT_Z Figure 2. MAX9324 CLK_EN Timing Diagram SEOUT_Z enables/disables the single-ended LVCMOS output (Table 1). Connect SEOUT_Z to GND to enable the single-ended output. Connect SEOUT_Z to V ...
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver SEOUT provides a single-ended LVCMOS monitor out- put. SEOUT operates with a maximum output frequency of 200MHz. Ensure that the output currents do not violate the cur- rent limits as specified in the ...
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One-to-Five LVPECL/LVCMOS Output Clock and 3.0V TO 3.6V 0.01µF 0.1µ 50Ω CLK 50Ω CLK O 50Ω 50Ω CLK_EN OFF OFF SEOUT_Z ON _______________________________________________________________________________________ 0.01µF 0.01µ ...
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) 10 ______________________________________________________________________________________ Package Information PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 ...
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One-to-Five LVPECL/LVCMOS Output Clock and (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) ______________________________________________________________________________________ Data Driver Package Information (continued) PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 ...
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One-to-Five LVPECL/LVCMOS Output Clock and Data Driver (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other ...