max9975 Maxim Integrated Products, Inc., max9975 Datasheet - Page 29

• Manufacturer Part Number: max9975
• Description: Max9975 Dual, Low-power, 1200mbps Ate Driver/comparator With 35ma Load
• Manufacturer: Maxim Integrated Products, Inc.

Figure
Figure
SCLK
RST
THR
DIN
CS
*USED FOR SLEW-RATE CONTROL ON MAX9969.
4. Serial Interface
5. Serial-Interface Timing
SCLK
20kΩ
DIN
CS
MAX9975
V
THRINT
5
7
0, 1, 4
7
______________________________________________________________________________________
= 1.25V
D
ENABLE
D
ENABLE
ENABLE
SET
F/F
F/F
t
CH
CHANNEL 1 MODE BITS
Q
Q
t
0
CSS0
TMSEL,
LDDIS,
CDIFF
3
1
D6
LLEAK
Driver/Comparator with 35mA Load
SHIFT REGISTER
2
1
3
5
6
0, 1, 4
6
t
Dual, Low-Power, 1200Mbps ATE
4
DS
D
ENABLE
D
ENABLE
D5
5
SET
F/F
F/F
t
DH
CHANNEL 2 MODE BITS
6
Q
Q
TMSEL,
LDDIS,
CDIFF
7
3
LLEAK
D4
1
t
CL
D3
the driver, clamps, and active load are disabled. This
mode is convenient for making IDDQ and PMU measure-
ments without the need for an output disconnect relay.
LLEAK is programmed independently for each channel.
When DUT_ is driven with a high-speed signal while
LLEAK is asserted, the leakage current momentarily
increases beyond the limits specified for normal opera-
tion. The low-leakage recovery specification in the
Electrical Characteristics table indicates device behav-
ior under this condition.
A CMOS-compatible serial interface controls the
MAX9975 modes (Figure 4 and Table 5). Control data
flow into an 8-bit shift register (MSB first) and are
latched when CS is taken high, as shown in Figure 5.
Latches contain 6 control bits for each channel of the
dual-pin driver. Data from the shift register are loaded
to either or both of the latches as determined by bits D6
and D7. When CDIFF = 1, its effect is independent of
bits D6 and D7. The control bits, in conjunction with
external inputs DATA_ and RCV_, manage the features
of each channel, as shown in Tables 1 and 2. RST sets
LLEAK = 1 for both channels, forcing them into low-
leakage mode. All other bits are unaffected. At power-
up, hold RST low until V
D2
Serial Interface and Device Control
D1
t
CSH1
CC
D0
and V
t
CSS1
t
CSWH
EE
have stabilized.
29