nb3n853501e ON Semiconductor, nb3n853501e Datasheet - Page 2

• Manufacturer Part Number: nb3n853501e
• Description: 3.3 V Lvttl/lvcmos 2 1 Mux To 4 Lvpecl Differential Clock Fanout Buffer Outputs With Clock Enable And Clock Select
• Manufacturer: ON Semiconductor

1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.
Table 1. PIN DESCRIPTION
Table 2. FUNCTIONS
11, 14, 16,
12, 15, 16,
10, 13, 18
5, 6, 8, 9
CLK_EN
Number
19
20
1
2
3
4
6
0
0
1
1
CLK_SEL
CLK_EN
CLK_SEL
Name
Q[3:0]
Q[3:0]
CLK0
CLK1
V
V
nc
EE
CC
0
1
0
1
Inputs
LVCMOS /
LVCMOS /
LVCMOS /
LVCMOS /
LVPECL
LVPECL
LVTTL
LVTTL
LVTTL
LVTTL
I/O
CLK_SEL
CLK1 Input Selected
CLK1 Input Selected
CLK0 input selected
CLK0 input selected
CLK_EN
Input Function
CLK0
CLK1
V
V
Figure 2. Pinout Diagram (Top View)
CC
EE
nc
nc
nc
nc
Pulldown
Pulldown
Pulldown
Default
Pullup
Open
http://onsemi.com
1
2
3
4
5
6
7
8
9
10
Negative (Ground) Power Supply pin must be externally connected to
power supply to guarantee proper operation.
Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW)
Clock Input Select (HIGH selects CLK1, LOW selects CLK0 input)
Clock 0 Input. Float open when unused.
No Connect
Clock 1 Input. Float open when unused.
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Invert Differential Outputs
True Differential Outputs
2
Output Function
20
19
18
17
16
15
14
13
12
11
Disabled
Disabled
Enabled
Enabled
Q0
Q0
V
Q1
Q1
Q2
Q2
V
Q3
Q3
CC
CC
Description
Outputs
CLK0
CLK1
LOW
LOW
Qx
Invert of
Invert of
HIGH
HIGH
CLK1
CLK1
Qx