nb3n853501e ON Semiconductor, nb3n853501e Datasheet

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nb3n853501e

Manufacturer Part Number
nb3n853501e
Description
3.3 V Lvttl/lvcmos 2 1 Mux To 4 Lvpecl Differential Clock Fanout Buffer Outputs With Clock Enable And Clock Select
Manufacturer
ON Semiconductor
Datasheet
NB3N853501E
3.3 V LVTTL/LVCMOS 2:1
MUX to 4 LVPECL
Differential Clock Fanout
Buffer Outputs with Clock
Enable and Clock Select
Description
fanout buffer. Input MUX selects one of two LVCMOS/LVTTL CLK
lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using
LVCMOS/LVTTL levels. Outputs are LVPECL levels and are
synchronously enabled by CLK_EN using LVCMOS/LVTTL levels
(HIGH to enable outputs, LOW to disable output).
Features
© Semiconductor Components Industries, LLC, 2011
November, 2011 − Rev. 2
The NB3N853501E is a pure 3.3 V supply 2:1:4 clock distribution
Four differential LVPECL Outputs
Two Selectable LVCMOS/LVTTL CLOCK Inputs
Up to 266 MHz Clock Operation
Output to Output Skew: 30 ps (Max.)
Device to Device Skew 250 ps (Max.)
Propagation Delay 2.0 ns (Max.)
Operating range: V
Additive Phase Jitter, RMS: 62 fs (Typ)
Synchronous Clock Enable Control
Industrial Temp. Range (−40
Pb−Free TSSOP20 Package
These are Pb−Free Devices
Figure 1. Simplified Logic Diagram
CC
= 3.3 ±5% V( 3.135 to 3.465 V)
°
C to 85
°
C)
1
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
(Note: Microdot may be in either location)
CASE 948E
DT SUFFIX
TSSOP−20
ORDERING INFORMATION
A
L
Y
W
G
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
NB3N853501E/D
MARKING
DIAGRAM
ALYWG
NB3N
501E
G

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nb3n853501e Summary of contents

Page 1

... Buffer Outputs with Clock Enable and Clock Select Description The NB3N853501E is a pure 3.3 V supply 2:1:4 clock distribution fanout buffer. Input MUX selects one of two LVCMOS/LVTTL CLK lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using LVCMOS/LVTTL levels. Outputs are LVPECL levels and are synchronously enabled by CLK_EN using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output) ...

Page 2

CLK_SEL Table 1. PIN DESCRIPTION Number Name I CLK_EN LVCMOS / LVTTL 3 CLK_SEL LVCMOS / LVTTL 4 CLK0 LVCMOS / LVTTL CLK1 LVCMOS / LVTTL 10, 13 ...

Page 3

Table 3. ATTRIBUTES Internal Input Pullup Resistor Internal Input Pulldown Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional ...

Page 4

Table 5. DC CHARACTERISTICS V Symbol I Power Supply Current EE V Input HIGH Voltage IH V Input LOW Voltage IL I Input High Current ( Input LOW Current ( Output HIGH Voltage OH ...

Page 5

Table 6. AC CHARACTERISTICS V Symbol F Maximum Operating Frequency MAX t Propagation Delay PD tSKEW Duty Cycle Skew same path similar conditions at 50 MHz DC tSKEW Output to Output Skew Within A Device O−O tSKEW Device−to−Device Skew similar ...

Page 6

Figure 5. AC Measurement Reference http://onsemi.com 6 ...

Page 7

... Figure 6. For 155.52 MHz carrier, the NB3N853501E Additive Phase Noise (dBc/Hz) verses SSB Offset Frequency (Hz) Integrated Jitter from 12 kHz to 20 MHz (Upper Heavy Line) is 93.3 fs RMS. The E8663B Source Generator Additive Phase Noise (Lower Light Line) is 70.1 fs RMS. Where t ORDERING INFORMATION ...

Page 8

... 0.100 (0.004) −T− SEATING PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE ...

Page 9

... N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 9 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB3N853501E/D ...

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