lv8104v Sanyo Semiconductor Corporation, lv8104v Datasheet
lv8104v
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lv8104v Summary of contents
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... LV8104V Overview The LV8104V is a pre-driver IC designed for variable speed control of 3-phase brushless motors. It can be used to implement both upper and low output N-channel power FET drive circuit using a built-in charge pump circuit. High-efficiency drive is possible through the use of direct PWM drive and synchronous rectifyication. ...
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... Common-mode input voltage range 2 VICM2 Hall input sensitivity ΔV IN (HA) Hysteresis width Input voltage Low → High VSLH Input voltage High → Low VSHL LV8104V Conditions pin Pins UL, VL, WL Pins UH, VH, WH, UOUT, VOUT and WOUT Independent IC Mounted on the specified board * Conditions ...
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... Low level output voltage V OL (C) Amplitude V (C) FIL pin Output source current I OH (FIL) Output sink current I OL (FIL) LV8104V Conditions IFGI = -0.1mA, No load IFGI = 0.1mA, No load GAIN : 100 times One-side hysteresis comparator 2kHz I FGS = 2mA 0.047μF VREG-1 ...
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... Hysteresis width V IS (BR) High level input current I IH (BR) Low level input current I IL (BR) Pull-up resistance RU (BR) Note : * These items are design target values and are not tested. LV8104V Conditions Design target value* Design target value* VREG-0.5 Design target value* VCLK = 5V VCLK = 0V VREG-0.5 ...
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... Specified board : 114.3 × 76.1 × 1.6mm Mounted on a board 1.7 1.5 1.0 Independent IC 0.65 0 — Ambient temperature, Ta Pin Assignment LV8104V 23 22 0.2 SANYO : SSOP44(275mil glass epoxy 0.95 0. 100 - LV8104 ...
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... S/S Input Input High or Open Low Current Control Characteristics LV8104V (A high level input is the state where IN + > F/R = “H” IN1 IN2 IN3 Input ...
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... Block Diagram (Referance constants) LV8104V No.A1677-7/19 ...
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... Relations Hall input with Drive output (1) When F/R = ”L” IN1 IN2 IN3 PWM control output (2) When F/R = ”H” IN1 IN2 IN3 PWM control output LV8104V Synchronous rectification output Synchronous rectification output No.A1677-8/19 ...
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... When F/R = ”L” and the inverting phase input as against Hall input(2). IN1 IN2 IN3 (4) When F/R=”H” and the inverting phase input as against Hall input(1). IN1 IN2 IN3 LV8104V PWM control output Synchronous rectification output PWM control output Synchronous rectification output No.A1677-9/19 ...
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... VCO oscillation pin. Connect a capacitor between this pin and GND Pin to set the charge / discharge current of the VCO circuit. Connect a resistor between this pin and GND. 6 FIL VCO PLL output filter pin. LV8104V Pin function V CC VREG VREG VREG 6 Equivalent circuit Continued on next page ...
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... Connect a capacitor between this pin and GND. 11 DOUT Speed discriminator output pin. Acceleration → high, deceleration → low. 12 POUT Speed control PLL output pin. Outputs the phase comparison result for CLK and FG. LV8104V Pin function VREG VREG 10 VREG VREG Equivalent circuit Reset circuit VREG 8 Continued on next page ...
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... Low : 0V to 1.0V High : 2.0V to VREG Goes high when left open. High or open for brake mode operation. The hysteresis width is about 0.27V. 17 FGS FG amplifier Schmitt output pin. This is an open collector output. LV8104V Pin function VREG VREG VREG VREG VREG Equivalent circuit 13 14 ...
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... If noise on the Hall signals is a problem, insert IN3 - capacitors between the corresponding IN + and IN3 + 27 inputs. 28 RFGND Output current detection reference pin. Connect to GND side of the current detection resistor Rf. LV8104V Pin function VREG VREG FG Schmitt comparator VREG 21 VREG VREG 28 ...
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... Connect a capacitor between this pin and GND for stabilization Charge pump output pin. Connect a capacitor between this pin and CP2 Pin to connect the capacitor for charge pump. Connect a capacitor between this pin and CP1. LV8104V Pin function VREG VREG VG 42 Equivalent circuit ...
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... Continued from preceding page. Pin No. Pin name 44 CP1 Pin to connect the capacitor for charge pump. Connect a capacitor between this pin and CP2 connection pins. 41 LV8104V Pin function Equivalent circuit No.A1677-15/19 ...
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... Description of LV8104V 1. Speed control circuit This IC controls the speed with a combination of the speed discriminator circuit and the PLL circuit. Therefore, when a motor that has large load variation is used possible to prevent the rotation variation as compared with the speed control method only the speed discriminator. The speed discriminator circuit and the PLL circuit outputs an error signal once every one FG period ...
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... CSD pin is stopped. The CSD pin combines also functions as the initial reset pin. The time that the CSD pin voltage is charged to about 1.25V is determined as the initial reset. At the initial reset, all the outputs will be in the off state. LV8104V No.A1677-17/19 ...
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... The capacitor connected between the FGIN + pin and GND is required for bias voltage stabilization. This capacitor must be connected to the GND1 pin (pin 3) with a line that is as short as possible to reduce influence of noise. As the FG amplifier and the FGS output are operating even if the S/S pin is the stop state possible to monitor the motor rotation by the FGS output. LV8104V No.A1677-18/19 ...
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... SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2010. Specifications and information herein are subject to change without notice. LV8104V PS No.A1677-19/19 ...