nb6n11s ON Semiconductor, nb6n11s Datasheet - Page 2

• Manufacturer Part Number: nb6n11s
• Description: 3.3 V 1 2 Anylevel Tm Input To Lvds Fanout Buffer /translator
• Manufacturer: ON Semiconductor

1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage
Table 1. PIN DESCRIPTION
or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self−oscillation.
Pin
EP
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Name
V
V
V
V
V
V
V
V
V
NC
Q0
Q0
Q1
Q1
D
D
CC
CC
CC
CC
CC
EE
EE
TD
TD
LVPECL, CML, LVDS,
LVPECL, CML, LVDS,
LVCMOS, LVTTL
LVCMOS, LVTTL
LVDS Output
LVDS Output
LVDS Output
LVDS Output
Figure 3. NB6N11S Pinout, 16−pin QFN
I/O
−
−
−
−
−
−
−
Q0
Q0
Q1
Q1
1
2
3
4
V
V
16
5
CC
CC
http://onsemi.com
Non−inverted D output. Typically loaded with 100 W receiver termination
resistor across differential pair.
Inverted D output. Typically loaded with 10 W receiver termination resistor
across differential pair.
Non−inverted D output. Typically loaded with 100 W receiver termination
resistor across differential pair.
Inverted D output. Typically loaded with 100 W receiver termination resistor
across differential pair.
Positive Supply Voltage
No Connect
Negative Supply Voltage
Negative Supply Voltage
Internal 50 W termination pin for D
Inverted Differential Clock/Data Input (Note 1)
Non−inverted Differential Clock/Data Input (Note 1)
Internal 50 W termination pin for D
Positive Supply Voltage
Positive Supply Voltage
Positive Supply Voltage
Positive Supply Voltage
Exposed pad. The exposed pad (EP) on the package bottom must be
attached to a heat−sinking conduit. The exposed pad may only be
electrically connected to V
V
NB6N11S
NB6N11S
15
NC
CC
6
2
V
V
14
7
CC
EE
V
13
V
8
CC
EE
12
10
11
9
(Top View)
EE
V
D
D
V
TD
TD
Exposed Pad (EP)
.
Description