lmk04000bisqx National Semiconductor Corporation, lmk04000bisqx Datasheet - Page 4

• Manufacturer Part Number: lmk04000bisqx
• Description: Lmk04000 Family Of Precision Clock Conditioners Low-noise Clock Jitter Cleaner With Cascaded Plls
• Manufacturer: National Semiconductor Corporation

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17.0 Application Information ................................................................................................................. 35
18.0 Physical Dimensions .................................................................................................................... 49
19.0 Ordering Information .................................................................................................................... 49
16.9 REGISTER 12 ........................................................................................................................... 31
16.10 REGISTER 13 ......................................................................................................................... 32
16.11 REGISTER 14 ......................................................................................................................... 33
16.12 REGISTER 15 ......................................................................................................................... 34
17.1 SYSTEM LEVEL DIAGRAM ........................................................................................................ 35
17.2 LDO BYPASS AND BIAS PIN ..................................................................................................... 36
17.3 LOOP FILTER ........................................................................................................................... 36
17.4 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS ........................................... 39
17.5 POWER SUPPLY CONDITIONING .............................................................................................. 39
17.6 THERMAL MANAGEMENT ......................................................................................................... 39
17.7 OPTIONAL CRYSTAL OSCILLATOR IMPLEMENTATION (OSCin/OSCin*) ...................................... 40
17.8 TERMINATION AND USE OF CLOCK OUTPUT (DRIVERS) ........................................................... 43
17.9 DRIVING CLKin AND OSCin INPUTS .......................................................................................... 45
17.10 ADDITIONAL OUTPUTS WITH AN LMK04000 FAMILY DEVICE ................................................... 45
17.11 OUTPUT CLOCK PHASE NOISE PERFORMANCE VS. VCXO PHASE NOISE ............................... 45
16.9.1 PLL1_N: PLL1_N Counter ...................................................................................................... 31
16.9.2 PLL1_R: PLL1_R Counter ...................................................................................................... 32
16.9.3 PLL1 Charge Pump Current Gain (PLL1_CP_GAIN) and Polarity Control (PLL1_CP_POL) ............. 32
16.10.1 EN_PLL2_XTAL: Crystal Oscillator Option Enable ................................................................... 32
16.10.2 EN_Fout: Fout Power Down Bit ............................................................................................. 32
16.10.3 CLK Global Enable: Clock Global enable bit ............................................................................ 32
16.10.4 POWERDOWN Bit -- Device Power Down .............................................................................. 32
16.10.5 EN_PLL2 REF2X: PLL2 Frequency Doubler control bit ............................................................. 32
16.10.6 PLL2 Internal Loop Filter Component Values .......................................................................... 32
16.10.7 PLL1 CP TRI-STATE and PLL2 CP TRI-STATE ...................................................................... 33
16.11.1 OSCin_FREQ: PLL2 Oscillator Input Frequency Register ......................................................... 33
16.11.2 PLL2_R: PLL2_R Counter .................................................................................................... 33
16.11.3 PLL_MUX: LD Pin Selectable Output ..................................................................................... 33
16.12.1 PLL2_N: PLL2_N Counter .................................................................................................... 34
16.12.2 PLL2_CP_GAIN: PLL2 Charge Pump Current and Output Control ............................................. 34
16.12.3 VCO_DIV: PLL2 VCO Divide Register .................................................................................... 34
17.8.1 Termination for DC Coupled Differential Operation .................................................................... 43
17.8.2 Termination for AC Coupled Differential Operation ..................................................................... 43
17.8.3 Termination for Single-Ended Operation ................................................................................... 44
17.9.1 Driving CLKin Pins with a Differential Source ............................................................................ 45
17.9.2 Driving CLKin Pins with a Single-Ended Source ........................................................................ 45
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