lmk04000b National Semiconductor Corporation, lmk04000b Datasheet - Page 32

• Manufacturer Part Number: lmk04000b
• Description: Low-noise Clock Jitter Cleaner With Cascaded Plls
• Manufacturer: National Semiconductor Corporation

www.national.com
16.2 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON/RESET
Table 2 illustrates the default register settings programmed in silicon for the LMK040xx after power on or asserting the reset bit.
Note 43: These registers are reserved. The Power On/Reset values for these registers are shown in the register map and should not be changed during
programming.
Note 44: If the CLKin_SEL value is set to either [0,0] or [0,1], the LOS_TYPE field should be set to [0,0].
Field Name
CLKoutX_PECL_LVL
CLKoutXB_STATE
CLKoutXA_STATE
EN_CLKoutX
Reserved Registers
RC_DLD1_Start
CLKin1_BUFTYPE
CLKin0_BUFTYPE
LOS_TIMEOUT
LOS_TYPE
CLKin_SEL
PLL1 CP Polarity
PLL1_CP_GAIN
PLL1_R Counter
PLL1_N Counter
EN_PLL2_REF2X
EN_PLL2_XTAL
EN_Fout
CLK Global Enable
POWER DOWN
PLL2 CP TRI-STATE
PLL1 CP TRI-STATE
OSCin_FREQ
PLL_MUX
PLL2_R Counter
PLL2_CP_GAIN
VCO_DIV
PLL2_N Counter
(decimal)
Default
Value
TABLE 2. Default Device Register Settings after Power On/Reset
200
31
0
0
1
0
1
1
1
1
3
0
1
6
1
1
0
0
0
1
0
0
0
1
2
2
1
2VPECL disabled This bit sets LVPECL clock level. Valid
Disabled (device
Positive polarity
Default State
Non-Inverted
3 MHz (min.)
TRI-STATE
TRI-STATE
MOS mode
MOS mode
Divide = 1
Divide = 1
Divide = 1
Divide = 2
Divide = 1
(Note 43)
Reserved
Disabled
is active)
200 MHz
Inverted
Enabled
Enabled
disabled
disabled
1600 µA
CLKin0
100 µA
CMOS
OFF
OFF
OFF
Field Description
when the clock channel is configured as
LVPECL/2VPECL; otherwise, not relevant.
This field sets the state of output B of an
LVCMOS Clock channel.
This field sets the state of output A of an
LVCMOS Clock channel.
Clock Channel enable bit. Note: The state
of CLKout2 is ON by default.
(Note 43)
Forces the VCO tuning algorithm state
machine to wait until PLL1 is locked.
CLKin1 Input Buffer Type
CLKin0 Input Buffer Type
Selects Lower Reference Clock input
frequency for LOS Detection.
Selects LOS output type (Note 44)
Selects Reference Clock source
Selects the charge pump output polarity,
i.e., the tuning slope of the external VCXO
Sets the PLL1 Charge Pump Gain
Sets divide value for PLL1_R Counter
Sets divide value for PLL1_N Counter
Enables or disables the OSCin frequency
doubler path for the PLL2 reference input
Enables or Disables internal circuits that
support an external crystal driving the
OSCin pins
Enables or disables the VCO output buffer
Global enable or disable for output clocks
Device power down control
Enables or disables TRI-STATE for PLL2
Charge Pump
Enables or disables TRI-STATE for PLL1
Charge Pump
Source frequency driving OSCin port
Selects output routed to LD pin
Sets Divide value for PLL2_R Counter
Sets PLL2 Charge Pump Gain
Sets divide value for VCO output divider
Sets PLL2_N Counter value
32
R5,R6,R8
Register
R0 to R4
R1 to R3
R1 to R3
R0 to R4
R9,R10
R10
R11
R11
R11
R11
R11
R12
R12
R12
R12
R13
R13
R13
R13
R13
R13
R13
R14
R14
R14
R15
R15
R15
Bit Location
(MSB:LSB)
22:21
20:19
30:28
27:16
28:21
20:16
27:26
25:22
15:4
15:4
21:4
NA
9:8
7:6
5:4
23
16
29
11
10
31
16
21
20
18
17
15
14