cy7b9532v Cypress Semiconductor Corporation., cy7b9532v Datasheet
cy7b9532v
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cy7b9532v Summary of contents
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... The CY7B9532V Transceiver’s parallel HSTL I/O can also be configured to operate at LVPECL signaling levels. This can all be done externally by changing V simple circuit at the termination of the receiver’s parallel I/O interface ...
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... PRELIMINARY CY7B9532V Logic Block Diagram (155.52 MHz) TXCLKI TXD[15:0] FIFO_ERR FIFO_RST 16 Input Register FIFO TX Bit-Clock Shifter LOOPTIME LINELOOP LOOPA OUT (155.52 MHz) REFCLK TXCLKO TX PLL X16 16 Recovered Bit-Clock Lock-to-Ref Lock-to-Data/ Clock Control Logic PWRDN LOCKREF SD LFI RESET 2 CY7B9532V (155.52 MHz) ...
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... PRELIMINARY Top View CY7B9532 Output Current into LVTTL Outputs (LOW) ................. Input Voltage ..................................... –0. Static Discharge Voltage (per MIL-STD-883, Method 3015) Latch-Up Current Operating Range Range Commercial +0.5V DDQ Industrial +0. CY7B9532V NC 90 VCCQ 89 VSSQ 88 REFCLK+ 87 REFCLK– LOOPTIME 84 PWRDN 83 ...
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... Pin Descriptions CY7B9532V OC-48 SONET Transceiver Name I/O Characteristics Transmit Path Signals TXDA[15:0] HSTL inputs, sampled by TXCLKI TXCLKI HSTL Clock input TXCLKO HSTL Clock output Receive Path Signals RXD[15:0] HSTL output, synchronous RXCLK HSTL Clock output Device Control and Status Signals REFCLK± ...
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... Pin Descriptions (continued) CY7B9532V OC-48 SONET Transceiver Name I/O Characteristics LOOPA LVTTL input LOOPTIME LVTTL input Serial I/O OUT± Differential CML output IN± Differential CML input Power V Power CCN V Ground SSN V CCQ V SSQ V DDQ CY7B9532 Operation The CY7B9532 is a highly configurable device designed to support reliable transfer of large quantities of data, using high- speed serial links ...
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... RESET and FIFO_RST sig- nals should be asserted LOW along with PWRDN signal to ensure low power dissipation. PECL Compliance The CY7B9532V HSTL parallel I/O can be configured to LVPECL compliance with slight termination modifications. On the transmit side of the transceiver, the TXD[15:0] and TXCLK can be made LVPECL compliant by setting V ...
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... Low = –3.0V High = 0 MHz MHz Test Conditions Test Conditions Max. IN IEHH Min. IN IELL 7 CY7B9532V Min. Max. = Min., 2.4 = –10 Min., 0 –20 –90 2.0 V – 0 0.5V CC –0.3 0.8 = Max Max. – Max Max. ...
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... OUT V = Max. DDQ DDQ V = Max. DDQ Max. DDQ @ MHz V = Max. DDQ @ MHz 8 CY7B9532V Min. Max. – 0.5 V – 0 – 1.1 V – 0 560 1500 280 750 125 600 250 1200 V CC 1.2 Max. 47 ICHH Min. 20 ICLL 4 Min ...
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... CML Output Rise Time (20–80%, 100 balanced load) RISE t CML Output Fall Time (80–20%, 100 balanced load) FALL t Total Output Jitter (p-p) TJ Total Output Jitter (rms) PRELIMINARY Description of TXCLKI of TXCLK of RXCLKO of RXCLKO Description Description 9 CY7B9532V Min. Max. Unit 154.5 156.5 MHz 6.38 6. 0.3 1.5 ns 0.3 1.5 ...
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... HSTL Input Test Waveform PRELIMINARY 3.3V R1 OUT+ R2 OUT– (b) CML AC Test Load 1. =1.4V th 20% 250 ps < (b) CML Input Test Waveform V =0.75V 20% th 250 ps < (d) LVPECL Input Test Waveform 10 CY7B9532V R =100 ICHH 80% 80% 20% V ICLL 250 ps V IEHH 80% 80% 20% V IELL 250 ps ...
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... RXD[15:0] & RXCLK R1 = 137, RPU = 80.6, RPD = 121 Figure 6. LVPECL Compliant Termination CY7B9532 Zo=50 0.1 F IN+ IN– 0.1 F Zo=50 Figure 2. Serial Input Termination CY7B9532 Zo=50 0.1 F OUT+ OUT– 0.1 F Zo=50 Figure 3. Serial Output Termination 1.5V R1 Zo=50 R2 Zo=50 Figure 5. RXD[15:0] Termination 3 RPU PECL INPUT RPD 11 CY7B9532V 100 HSTL INPUT HSTL INPUT ...
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... Receive Interface Timing RXCLK RXD[15:0] Ordering Information Speed Ordering Code Package Name Standard CY7B9532-AC Standard CY7B9532-AI Document #: 38-00894 PRELIMINARY t TXCLK t TXCLKH TXCLKL t TXDS t RXCLKP t t RXCLKH RXCLKL t RXDS Package Type A120 120-pin TQFP A120 120-pin TQFP 12 CY7B9532V t TXDH t RXDH Operating Range Commercial Industrial ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7B9532V 51-85100 ...