cy7b9234 Cypress Semiconductor Corporation., cy7b9234 Datasheet - Page 5

• Manufacturer Part Number: cy7b9234
• Description: Smpte Hotlink Transmitter/receiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02014 Rev. *A
CY7B9234 SMPTE HOTLink Transmitter Block
Diagram Description
Input Register
The Input register holds the data to be processed by the
SMPTE HOTLink transmitter and allows the input timing to be
made consistent with standard FIFOs. The Input register is
clocked by CKW and loaded with information on the D
SC/D, and SVS pins. Two enable inputs (ENA and ENN) allow the
user to choose when data is loaded in the register. Asserting ENA
(Enable, active LOW) causes the inputs to be loaded in the register
on the rising edge of CKW. If ENN (Enable Next, active LOW) is
asserted when CKW rises, the data present on the inputs on the
next rising edge of CKW will be loaded into the Input register. If
neither ENA nor ENN are asserted LOW on the rising edge of CKW,
then a SYNC (K28.5) character is sent. These two inputs allow
proper timing and function for compatibility with either
asynchronous FIFOs or clocked FIFOs without external logic, as
shown in Figure 5.
In BIST mode, the Input register becomes the signature
pattern generator by logically converting the parallel Input
register into a Linear Feedback Shift Register (LFSR). When
enabled, this LFSR will generate a 511-byte sequence that
includes all Data and Special Character codes, including the
explicit violation symbols. This pattern provides a predictable
but pseudo-random sequence that can be matched to an
identical LFSR in the Receiver.
Encoder
The Encoder transforms the input data held by the Input
register into a form more suitable for transmission on a serial
interface link. The code used is specified by ANSI X3.230
(Fibre Channel), IBM ESCON® channel (code tables are at
the end of this datasheet), and the DVB-ASI serial interface.
The eight D
or a Special Character, depending upon the state of the SC/D input.
If SC/D is HIGH, the data inputs represent a control code and are
encoded using the Special Character code table. If SC/D is LOW,
the data inputs are converted using the Data code table. If a byte
time passes with the inputs disabled, the Encoder will output a
Special Character Comma K28.5 (or SYNC) that will maintain link
synchronization. SVS input forces the transmission of a specified
Violation symbol to allow the user to check error handling system
logic in the controller or for proprietary applications.
The 8B/10B coding function of the Encoder can be bypassed
for SMPTE systems that include an external coder or
scrambler function as part of the controller. This bypass is
controlled by setting the MODE select pin HIGH. When in
bypass mode, D
Channel 8B/10B code) become the ten inputs to the Shifter, with D
being the first bit to be shifted out.
Shifter
The Shifter accepts parallel data from the Encoder once each
byte time and shifts it to the serial interface output buffers using
a PLL multiplied bit clock that runs at ten (10) times the byte
clock rate. Timing for the parallel transfer is controlled by the
counter included in the Clock Generator and is not affected by
signal levels or timing at the input pins.
OutA, OutB, OutC
The serial interface PECL output buffers (ECL100K refer-
enced to +5V) are the drivers for the serial media. They are all
connected to the Shifter and contain the same serial data. Two
of the output pairs (OUTA± and OUTB±) are controllable by the
0−7
data inputs are converted to either a Data symbol
a−j
(note that bit order is specified in the Fibre
0−7
a
,
FOTO input and can be disabled by the system controller to force a
logical zero (i.e., “light off”) at the outputs. The third output pair
(OUTC±) is not affected by FOTO and will supply a continuous data
stream suitable for loop-back testing of the subsystem.
OUTA± and OUTB± will respond to FOTO input changes within a
few bit times. However, since FOTO is not synchronized with the
transmitter data stream, the outputs will be forced off or turned on at
arbitrary points in a transmitted byte. This function is intended to
augment an external laser safety controller and as an aid for
Receiver PLL testing.
In wire-based systems, control of the outputs may not be
required, and FOTO can be strapped LOW. The three outputs
are intended to add system and architectural flexibility by
offering identical serial bit-streams with separate interfaces for
redundant connections or for multiple destinations. Unneeded
outputs can be wired to V
unused output circuitry.
Clock Generator
The clock generator is an embedded phase-locked loop (PLL)
that takes a byte-rate reference clock (CKW) and multiplies it
by ten (10) to create a bit rate clock for driving the serial shifter.
The byte rate reference comes from CKW, the rising edge of
which clocks data into the Input register. This clock must be a
crystal referenced pulse stream that has a frequency between
the minimum and maximum specified for the SMPTE HOTLink
Transmitter/Receiver pair. Signals controlled by this block form
the bit clock and the timing signals that control internal data
transfers between the Input register and the Shifter.
The read pulse (RP) is derived from the feedback counter used in
the PLL multiplier. It is a byte-rate pulse stream with the proper
phase and pulse widths to allow transfer of data from an
asynchronous FIFO. Pulse width is independent of CKW duty
cycle, since proper phase and duty cycle is maintained by the PLL.
The RP pulse stream will insure correct data transfers between
asynchronous FIFOs and the transmitter input latch with no external
logic.
Test Logic
Test logic includes the initialization and control for the Built-In
Self-Test (BIST) generator, the multiplexer for Test mode clock
distribution, and control logic to properly select the data
encoding. Test logic is discussed in more detail in the
CY7B9234 SMPTE HOTLink Transmitter Operating Mode
Description.
CY7B9334 SMPTE HOTLink Receiver Block
Diagram Description
Serial Data Inputs
Two pairs of differential line receivers are the inputs for the
serial data stream. INA± or INB± can be selected with the A/B
input. INA± is selected with A/B HIGH and INB± is selected with A/B
LOW. The threshold of A/B is compatible with the ECL 100K signals
from PECL fiber-optic interface modules or active equalizers. TTL
logic elements can be used to select the A or B inputs by adding a
resistor pull-up to the TTL driver connected to A/B. The differential
threshold of INA± and INB± will accommodate wire interconnect
with filtering losses or transmission line attenuation greater than 20
dB (V
interface modules (any ECL logic family, not limited to ECL 100K).
The common mode tolerance will accommodate a wide range of
signal termination voltages. The highest HIGH input that can be
DIF
> 50 mV) or can be directly connected to fiber-optic
CC
to disable and power down the
CY7B9234
CY7B9334
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