cy7b933 Cypress Semiconductor Corporation., cy7b933 Datasheet
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cy7b933
Manufacturer Part Number
cy7b933
Description
Hotlink? Transmitter/receiver
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
1.CY7B933.pdf
(33 pages)
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Cypress Semiconductor Corporation
Document #: 38-02017 Rev. *E
Features
• Fibre-Channel-compliant
• IBM ESCON
• DVB-ASI-compliant
• ATM-compliant
• 8B/10B-coded or 10-bit unencoded
• Standard HOTLink
• High-speed HOTLink: 160–400 Mbps for high-speed
• Low-speed HOTLink: 150–160 Mbps for low-cost fiber
• TTL synchronous I/O
• No external phase locked-loop (PLL) components
• Triple PECL 100K serial outputs
• Dual PECL 100K serial inputs
• Low power: 350 mW (Tx), 650 mW (Rx)
• Compatible with fiber-optic modules, coaxial cable, and
• Built-in Self-Test (BIST)
• Single +5V supply
• 28-pin SOIC/PLCC/LCC
• Pb-Free Packages Available
• 0.8µ BiCMOS
applications
applications
twisted pair media
CY7B923 Transmitter Logic Block Diagram
BISTEN
MODE
CKW
RP
-compliant
GENERATOR
CLOCK
LOGIC
ENN
TEST
: 160–330 Mbps
ENA
(D
D
INPUT REGISTER
b–h
0–7
)
ENCODER
ENABLE
SHIFTER
SC/D (D a )
SVS(D j )
•
FOTO
198 Champion Court
OUTA
OUTB
OUTC
INB (INB+)
CY7B933 Receiver Logic Block Diagram
HOTLink
SI(INB− )
REFCLK
Functional Description
The CY7B923 HOTLink
Receiver are point-to-point communications building blocks
that transfer data over high-speed serial links (fiber, coax, and
twisted pair). Standard HOTLink data rates range from 160 to
330 Mbits/second. Higher speed HOTLink is also available for
high-speed applications (160–400 Mbits/second), as well as,
for
Mbits/second operations). Figure 1 illustrates typical connec-
tions to host systems or controllers.
Eight bits of user data or protocol information are loaded into
the HOTLink transmitter and are encoded. Serial data is
shifted out of the three differential positive ECL (PECL) serial
ports at the bit rate (which is ten times the byte rate).
The HOTLink receiver accepts the serial bit stream at its differ-
ential line receiver inputs and, using a completely integrated
PLL Clock Synchronizer, recovers the timing information
necessary for data reconstruction. The bit stream is deseri-
alized, decoded, and checked for transmission errors.
Recovered bytes are presented in parallel to the receiving host
along with a byte-rate clock.
The 8B/10B encoder/decoder can be disabled in systems that
already encode or scramble the transmitted data. I/O signals
are available to create a seamless interface with both
asynchronous FIFOs (i.e., CY7C42X) and clocked FIFOs (i.e.,
CY7C44X). A BIST pattern generator and checker allows
testing of the transmitter, receiver, and the connecting link as
a part of a system diagnostic check.
HOTLink devices are ideal for a variety of applications where
a parallel interface can be replaced with a high-speed
point-to-point serial link. Applications include interconnecting
workstations, servers, mass storage, and video transmission
equipment.
BISTEN
MODE
INA+
INA−
A/B
SO
RF
low-cost
•
LOGIC
San Jose
TEST
PECL
TTL
applications,
CLOCK
SYNC
Transmitter/Receiver
,
CKR
CA 95134-1709
‚
Transmitter and CY7B933 HOTLink
DATA
RDY
Revised August 29, 2005
HOTLink-155
(Q
DECODER
REGISTER
DECODER
REGISTER
FRAMER
SHIFTER
OUTPUT
Q
b–h
0–7
)
SC/D (Q a )
•
CY7B923
CY7B933
408-943-2600
RVS(Q j )
(150–160
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