cy7b995ait Cypress Semiconductor Corporation., cy7b995ait Datasheet - Page 9

• Manufacturer Part Number: cy7b995ait
• Description: 2.5/3.3v 200-mhz High-speed Multi-phase Pll Clock Buffer
• Manufacturer: Cypress Semiconductor Corporation.

AC Timing Definitions
With PE HIGH (LOW), the REF rising (falling) edges are aligned
to the FB rising (falling) edges. Also, when PE is HIGH (LOW),
all divided outputs’ rising (falling) edges are aligned to the rising
(falling) edges of the undivided, non-inverted outputs.
Regardless of PE setting, divide-by-4 outputs’, rising edges align
to the divide-by-2 outputs’ rising edges.
Document #: 38-07337 Rev. *D
DIVIDE BY 2 OUTPUT
DIVIDE BY 4 OUTPUT
INVERTED Q
OTHER Q
REF
FB
Q
t
PD
t
PWH
t
REF
t
t
t
SKEWPR
SKEW0,1
SKEW1,3,4
Figure 2. Timing Definition
t
SKEW3
t
0DCV
t
SKEW1
In cases where a non-divided output is connected to the FB input
pin, the divided output rising edges can be either 0 or 180
degrees phase aligned to the REF input rising edges (as set
randomly at power-up). If the divided outputs are required as
rising-edge (falling-edge) aligned to the REF input’s rising
(falling) edge, set the PE pin HIGH (LOW) and connect the
lowest frequency divided output to the FB input pin. This setup
provides a consistent input-output and output-output phase
relationship.
t
t
SKEWPR
t
PWL
SKEW0,1
t
0DCV
t
SKEW1
t
SKEW3
RoboClock
t
SKEW3
t
CCJ1-12
®
t
SKEW1,3,4
, CY7B995
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