cy7b991v-5jit Cypress Semiconductor Corporation., cy7b991v-5jit Datasheet - Page 8

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cy7b991v-5jit

Manufacturer Part Number
cy7b991v-5jit
Description
Low Voltage Programmable Skew Clock Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Figure 8
downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay)
necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulate
low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in a
series.
Maximum Ratings
Operating outside these boundaries may affect the performance
and life of the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Output Current into Outputs (LOW) ............................. 64 mA
Document Number: 38-07141 Rev. *C
SYSTEM
CLOCK
shows the CY7B991V connected in series to construct a zero skew clock distribution tree between boards. Delays of the
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
FB
REF
FS
Figure 8. Board-to-Board Clock Distribution
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
Static Discharge Voltage............................................ >2001V
(MIL-STD-883, Method 3015)
Latch up Current...................................................... >200 mA
Operating Range
Commercial
Industrial
Range
L4
L1
L2
L3
Z
Ambient Temperature
0
–40°C to +85°C
0°C to +70°C
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Z
Z
Z
0
0
0
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
3.3V RoboClock
LOAD
LOAD
LOAD
CY7B991V
LOAD
3.3V ±
3.3V ±
10%
10%
V
CC
LOAD
Page 8 of 14
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