cy7b991v-5jit Cypress Semiconductor Corporation., cy7b991v-5jit Datasheet - Page 4

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cy7b991v-5jit

Manufacturer Part Number
cy7b991v-5jit
Description
Low Voltage Programmable Skew Clock Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, allowing the
CY7B991V to operate as explained in the
Description”
level inputs can have a removable jumper to ground or be tied
LOW through a 100W resistor. This enables an external tester to
change the state of these pins.
Note
Document Number: 38-07141 Rev. *C
4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).
(N/A)
(N/A)
(N/A)
(N/A)
on page 3. For testing purposes, any of the three
1Fx
2Fx
MM
MH
HM
LM
LH
ML
HL
HH
LL
Figure 1. Typical Outputs with Fb Connected to a Zero Skew Output Test Mode
LL/HH
(N/A)
(N/A)
(N/A)
(N/A)
3Fx
4Fx
MM
MH
HM
HH
LM
LH
ML
HL
REFInput
FBInput
DIVIDED
INVERT
– 6t
– 4t
– 3t
– 2t
– 1t
+1t
+2t
+3t
+4t
+6t
0t
U
U
U
U
U
U
U
U
U
U
U
“Block Diagram
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly controls all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function select
inputs (xF0 and xF1) and the waveform characteristics of the
REF input.
3.3V RoboClock
[4]
CY7B991V
Page 4 of 14
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