bbt3821 Intersil Corporation, bbt3821 Datasheet - Page 42

• Manufacturer Part Number: bbt3821
• Description: Octal Multi-rate Lx4/cx4 - Xaui Re-timer
• Manufacturer: Intersil Corporation

Note (1): These values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): PCS loopback via bit 3.0.14 (Table 57) is NOT permitted by IEEE 802.3ae-2002 for 10GBASE-X PCS devices. Many XENPAK hosts, however, expect this
Note (3): These bits are overridden by PCS XAUI_EN, see also Table 65.
Note (4): This state machine is implemented according to IEEE 802.3ae-2002 clause 48.2.6.
Note (1): “D” is either 3 for PCS or 4 for PHY XS. Behavior of the two devices is entirely independent of each other.
Note (1): The value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): These bits are overridden to FE’h by XAUI_EN, see Table 64 and Table 65.
Note (1): The value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
3.49153.6
3.49153.5
3.49153.4
3.49153.3
3.49153.2:0
BITS OVERRIDDEN BY XAUI_EN Bit, D.49153.11 (D.C001’h.11) = 1’b
D.49153.5
D.49153.6
D.49152.1
D.49152.4
D.49152.7
D.49154
3.49154.15:8
3.49154.7:0
3.49155.15:8
3.49155.7:0
REG. BIT
BIT
loopback (which is mandatory for 10GBASE-R PCS devices). Setting this bit will enable this loopback, but cause the BBT3821 to be non-conforming to the
current 802.3 specification. See “Loopback Modes ” on page 13).
BIT
BIT
(1)
TRANS_EN
AKR_SM_EN
A_ALIGN_DIS
PCS_SYNC_EN
DSKW_SM_EN
ERROR Code
PCS AKR_SM_EN
PCS TRANS_EN
Reserved
TX_SDR
Reserved
Reserved
PCS ERROR
Reserved
PCS XG_IDLE
NAME
NAME
NAME
NAME
42
Table 65. PCS or PHY XS XAUI_EN CONTROL OVERRIDE FUNCTIONS
Desired Value
Desired Value
1 = enable
1 = enable
0 = enabled
1 = enable
1 = enable
FE’h
Table 66. PCS INTERNAL ERROR CODE REGISTER
Table 64. PCS CONTROL REGISTER 3 (Continued)
MDIO REGISTER, ADDRESS = 3.49154 (3.C002’h)
Table 67. PCS INTERNAL IDLE CODE REGISTER
MDIO REGISTER ADDRESS = 3.49153 (3.C001’h)
MDIO REGISTER ADDRESS = 3.49155 (3.C003’h)
1 = enable random
A/K/R
0 = /K/ only
1 = enable
0 = disable
Overridden by
XAUI_EN, see
Table 65
PCS receive
data rate
SETTING
SETTING
OVERRIDE TO
SETTING
(2)
(3)
(3)
BBT3821
FE’h
07’h
DEFAULT
DEFAULT
DEFAULT
0’b
0’b
0’b
001’b
0’b
0’b
1’b
0’b
0’b
FE’h
DEFAULT
(1)
(1)
(1)
(1)
(1)
(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enable pseudo- random A/K/R
(IPG) on PCS transmitter side (vs. /K/ only)
This bit enables the transceiver to translate an “IDLE”
pattern in the internal FIFOs (matching the value of
register 3.C003’h) to and from the XAUI IDLE /K/
comma character or /A/, /K/ & /R/ characters.
1 = PCS egress takes data from PHY XS at half speed
0 = PCS egress takes data from PHY XS at full speed
Translates /A/K/R/ to-from /I/
Generate pseudo-random /A/K/R/
Aligns data on incoming “||A||”
IEEE Clause 48.2.6 State Machine
IEEE Clause 48.2.6 State Machine
Internal FIFO ERROR character
Error Code. These bits allow the internal FIFO
ERROR control character to be programmed.
IDLE pattern in internal FIFOs for translation
to/from XAUI IDLEs
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
(4)
in Inter Packet Gap