pckv857 NXP Semiconductors, pckv857 Datasheet
pckv857
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pckv857 Summary of contents
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... PCKV857 70–190 MHz differential 1:10 clock driver Product data Supersedes data of 2001 Dec 03 hilips Semiconductors INTEGRATED CIRCUITS 2002 Sep 13 ...
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... V V and 2 differential data input and output levels. The PCKV857 is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs ( The clock outputs are controlled by the clock ...
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... OUT Y GND GND Product data PCKV857 DESCRIPTION SSTL_2 ground pins SSTL_2 differential outputs SSTL_2 power pins SSTL_2 differential inputs Analog power Analog ground Power-down control input 6 GND PWRDWN OUT ...
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... – – – – – – – – FB OUT 33 – FB OUT SW00692 4 Product data PCKV857 PLL ON/OFF PLL ON/OFF FB FB OUT OUT OFF OFF ...
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... CLK, FB Note 3 0.36 IN CLK, FB Note 3 0.7 IN Note DDQ Note DDQ — — and is the voltage at which the differential signals must be crossing Product data PCKV857 LIMITS UNIT UNIT MIN MAX 0.5 3.6 V 0.5 3.6 V –0.5 V 0.5 V DDQ –0.5 V 0.5 V DDQ — — ...
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... MHz to 190 MHz MHz to 190 MHz 2 GND DDQ and is the voltage at which the differential signals must be crossing. DDQ PARAMETER 6 Product data PCKV857 LIMITS UNIT UNIT MIN TYP MAX — — 1.2 V 0.1 — — V DDQ 1.7 — — ...
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... SSTV16857 SSTV16857 The PLL clock distribution device and SSTL registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation 7 Product data PCKV857 LIMITS UNIT UNIT MIN TYP MAX –150 0 150 ps — ...
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... AND OUTPUTS 2002 Sep large number of samples) (O) N Figure 1. Static phase offset t sk(O) Figure 2. Output skew 80 SLR(I) SLR(O) SLR(I) SLR(O) Figure 3. Input and output slew rates 8 Product data PCKV857 t (O SW00882 SW00883 80 20% SW00886 ...
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... JIT(CC) cycle n cycle n+1 Figure 5. Cycle-to-cycle jitter t t half period n half period – JIT(HPER) half period n 2*f O Figure 6. Half-period jitter skew ANY TWO OUTPUTS Figure 7. Skew between any two outputs. 9 Product data PCKV857 SW00884 SW00881 SW00885 SW00396 ...
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... Figure 8. Duty cycle limits and measurement – – NOTE: V Figure 9. Output load test circuit 10 Product data PCKV857 SW00397 SCOPE GND TT SW00880 ...
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... Philips Semiconductors 70–190 MHz differential 1:10 clock driver TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm 2002 Sep 13 11 Product data PCKV857 SOT362-1 ...
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... Philips Semiconductors 70–190 MHz differential 1:10 clock driver TSSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm 2002 Sep 13 12 Product data PCKV857 SOT480-1 ...
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... Philips Semiconductors 70–190 MHz differential 1:10 clock driver VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4 0.65 mm 2002 Sep 13 13 Product data PCKV857 SOT702-1 ...
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... Product data (9397 750 10343); fourth version supersedes Product data 2001 Dec 03. Engineering Change Notice 853-2242 28874 (2002 Sep 09). Modifications: Add new package option (VFBGA) to existing product data sheet. _3 2001 Dec 03 Product data (9397 750 09244); third version 2002 Sep 13 14 Product data PCKV857 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors 2002 Sep 13 Copyright Philips Electronics North America Corporation 2002 All rights reserved. Printed in U.S.A. Document order number: 15 Product data PCKV857 Date of release: 09-02 9397 750 10343 ...