pck857 NXP Semiconductors, pck857 Datasheet - Page 2

• Manufacturer Part Number: pck857
• Description: 66-150mhz Phase Locked Loop Differential 1 10 Sdram Clock Driver
• Manufacturer: NXP Semiconductors

FEATURES
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DESCRIPTION
Zero delay buffer to distribute an SSTL differential clock input pair to
10 SSTL_2 differential output pairs. Outputs are slope controlled.
External feedback pin for synchronization of the outputs to the input.
A CMOS style Enable/Disable pin is provided for low power disable.
ORDERING INFORMATION
Philips Semiconductors
2003 Jul 31
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
1-to-10 differential clock distribution
Very low skew (< 100 ps) and jitter (< 100 ps)
3 V AV
SSTL_2 interface clock inputs and outputs
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Full DDR solution provided when used with SSTL16857 and
CBT3857
50-150 MHz differential 1:10 SDRAM clock driver
48-Pin Plastic TSSOP
CC
PACKAGES
and 2.5 V V
CC
TEMPERATURE RANGE
0 to +85 °C
2
PIN CONFIGURATION
ORDER CODE
PCK857DGG
AGND
AV
GND
GND
GND
GND
GND
V
V
V
CLK
CLK
V
V
CC
CC
CC
CC
CC
Y
Y
Y
Y
Y
Y
CC
Y
Y
Y
Y
0
0
1
1
2
2
3
3
4
4
10
11
12
13
14
15
16
17
18
19
21
22
23
24
7
20
1
2
3
4
5
6
8
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
25
26
DRAWING NUMBER
GND
Y
Y
V
Y
Y
GND
GND
Y
Y
V
G
FBIN
FBIN
V
FBOUT
FBOUT
GND
Y
Y
V
Y
Y
GND
5
5
CC
6
6
7
7
CC
CC
8
8
CC
9
9
SW00358
SOT362-1
853-2199 23880
PCK857
Product data