pck2111 NXP Semiconductors, pck2111 Datasheet - Page 6

• Manufacturer Part Number: pck2111
• Description: Pck2111 1 10 Lvds Clock Distribution Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
CONTROL REGISTER SPECIFICATION
The PCK2111 is provided with an 11-bit shift register with a serial-in
and a Control Register. The purpose is to enable or power-off each
output clock channel and to select the clock input. The PCK2111
provides two working modes: Programmed mode, and Standard
mode.
Programmed Mode (EN = 1)
The shift register has a serial input to load the working configuration.
Once the configuration is loaded with 11 clock pulses, another clock
pulse loads the configuration into the Control Register. To restart the
configuration of the shift register, a reset of the state machine must
be done with a clock pulse on CK, and the EN set to LOW. The
Control Register can be configured only one time after each reset.
D0 is the first bit shifted in, D10 is the last bit shifted in. Bit D0
controls Q9, D9 controls Q0, and D10 controls CLKIN.
Standard Mode (EN = 0)
In Standard Mode, the PCK2111 is not programmable. All clock
buffer outputs are enabled. The LVDS clock input is selected from
Clock0 or Clock1 with the SI pin, as shown in the Truth Table.
Table 2. Configuration of the Control Register
Table 3. Truth Table of the Control Register
X = Don’t Care
AC ELECTRICAL CHARACTERISTICS (Control Register)
2002 Dec 16
Control Register bit
SYMBOL
1:10 LVDS clock distribution device
f
t
MAX
rem
t
t
t
w
h
s
Function
Maximum frequency of shift register
Clock to SI setup time
Clock to SI hold time
Enable to clock removal time
Minimum clock pulse width
D10
H
X
L
D0
Q9
PARAMETER
Q8
D1
D2
Q7
D3
Q6
Dn[0:9]
Q5
D4
H
H
L
6
CONDITIONS
Table 1. Truth Table of State Machine Inputs
EN
H
H
L
L
L
D5
Q4
SI
H
H
X
L
L
Q3
D6
MIN
50
—
—
—
CK
5
X
X
D7
Q2
All outputs enabled,
Clock0 selected,
Control Register disabled.
All outputs enabled,
Clock1 selected,
Control Register disabled.
First stage stores “L”, other
stages store the data of
previous stage.
First stage stores “H”, other
stages store the data of
previous stage.
Reset of the state machine,
Shift register, and Control
Register.
Qn output disabled
TYP
—
—
—
—
—
D8
Q1
Qn[0:9]
Clock0
Clock1
OUTPUT
Q0
D9
MAX
PCK2111
4.0
1.0
4.0
—
—
Product data
CLK_SEL
D10
UNIT
MHz
ns
ns
ns
ns