vsc880 Vitesse Semiconductor Corp, vsc880 Datasheet - Page 5

• Manufacturer Part Number: vsc880
• Description: High Performance 16x16 Serial Crosspoint Switch Semiconductor Corporation
• Manufacturer: Vitesse Semiconductor Corp

G52191-0, Rev 4.2
01/05/01
Data Sheet
VSC880
1.1.2 Data Scrambling
serial data links. All command words and connection request words contain this required density. In order to get this
density on data words, scrambling must be employed by the transceiver (see VSC870 data sheet).
1.1.3 Bit Synchronization
reference clock by 34 to generate a 2.125GHz clock and uses this clock to serialize the 32-bit word and 2 overhead
bits. The transceiver receives and feeds this serial data stream to a digital CRU to recover the bit clock and
deserialize the data stream to a 32-bit word plus 2 overhead bits at 62.5MHz. The transceiver also uses this recovered
clock to serialize its transmit words that are sent to the switch. In this way, the switch and all the transceivers are
frequency-locked to one clock source which is provided by the reference clock on the switch card. Because of this,
the switch chip needs to recover only the phase information on the serial receive channel using a data recovery unit
(DRU). The DRU is designed as a delay lock loop and remains phase-locked to the incoming data stream as long as
the temperature does not change by more than 20°C after link initialization. If this temperature variation is exceeded,
a link error may occur causing the link to reinitialize. Because of this, system reset should be held until the system
reaches temperature stability before starting the link initializing process.
1.1.4 Word Synchronization
sends reset patterns to the switch to request that the switch starts the initialization process. The switch, upon
receiving this request, will send out special ALIGN words. The transceiver receives this serial data stream and word
aligns to this ALIGN word by adjusting its own word boundary one bit at a time. Upon detecting the correct word
alignment, it starts the transmit word alignment process. In this process, the transceiver continuously sends ALIGN
words to the switch. The switch uses its own word clock (REFCLK) to detect this ALIGN word. If the transmitters
word is not aligned to the switch chip word clock when it arrives at the switch, the switch chip continues to send out
ALIGN words. After receiving 32 ALIGN words from the switch chip, the transceiver changes its transmit word
boundary by 1 bit position and repeats the process (this limits the distance from the transceiver to the switch to less
than 180ns one way). If the switch detects the transceivers ALIGN word correctly, it sends IDLE words to the
transceiver to signal that the transmitter has now word synchronized with the switch. It also clears the internal
registers LERR, TERR, DERR and CERR and sets the signal INT HIGH if all the enabled serial channels are
successfully initialized (see section 1.4).
1.1.5 Cell Synchronization
synchronization process. In this process, the transceiver detects the received cell clock (CCLK) sent from the switch
embedded in the alignment word. The switch delays the global cell clock to adjust out the pipeline delay from the
transceiver to the switch. The switch chip does this by connecting each port to itself during link initialization. By
sending an ALIGN words to itself, the transceiver can adjust the transmit clock until it is properly phase shifted
relative to the global cell clock. If cells are sent from the transceiver aligned to this transmit cell clock, they will
arrive at the switch aligned to the master cell clock which is originated at the switch. For this alignment process to
work, the minimum cell size is 8 words (32 bytes).
To allow the VSC870 CRU to recover the bit clock, a 15% edge transition density must be guaranteed on the
In Packet Mode and Cell Mode, the switch acts as the source of the bit clock. It multiplies the local 62.5MHz
If CMODE is set HIGH, after the word synchronization process completes, the transceiver starts the cell
During power up or at reset, the transceiver can initiate the word synchronization process. First, the transceiver
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High Performance 16x16
Serial Crosspoint Switch
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