vsc8061 Vitesse Semiconductor Corp, vsc8061 Datasheet - Page 8

• Manufacturer Part Number: vsc8061
• Description: 2.5gb/s 16-bit Multiplexer/demultiplexer Chipset
• Manufacturer: Vitesse Semiconductor Corp

Page 8
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
Coupling for Inputs
DCLK, DCLKN Inputs
ment inputs. This input can either be DC-coupled or AC-coupled; it can also be driven single-ended or differen-
tially. Figure 7 shows the configuration for a single-ended, AC-coupling operation. In the case of direct
coupling and single-ended input, it is recommended that a stable V
mentary input.
High-Speed Clock and Serial Data Inputs
and CLK/CLKN for the VSC8062) be AC-coupled. Figure 8 shows the configuration for a single-ended AC-
coupling operation.
where this does not hold, direct DC connection is possible. The following is to assist in this application.
is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part,
the mid-point of the input signal swing should be centered about this reference voltage and not exceed the max-
imum allowable amplitude. For single-ended, DC-coupling operations, it is recommended the user provide an
external reference voltage which has better temperature and power supply noise rejection than the on-chip resis-
tor divider. The external reference should have a nominal value as indicated in the table and can be connected to
either side of the differential gate.
C
C
(Capacitor values are selected for DCLK = 155Mb/s.)
Internal biasing will position the reference voltage of approximately -1.32V on both the true and comple-
It is recommended that all high-speed clock and serial data inputs (CLK/CLKN for the VSC8061; DI/DIN
In most situations, these inputs will have high transition density and little DC offset. However, in cases
All serial data and clock inputs have the same circuit topology, as shown in Figure 8. The reference voltage
IN
SE
typ = 0.1 F
typ = 0.1 F for single-ended applications
Z
R
O
T
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
= Z
O
Figure 7: AC-Coupling for DCLK, DCLKN Inputs
V
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
TT
C
V
TT
IN
C
VITESSE
SEMICONDUCTOR CORPORATION
SE
DCLKN
DCLK
Chip Boundary
Internet: www.vitesse.com
-1.32V
V
V
CC
TT
= GND
= -2V
-1.32V
REF
for ECL levels be used for the comple-
VSC8061/VSC8062
R
| |
= 1k
Data Sheet
G52069-0, Rev 4.3
05/11/01