vsc8124 Vitesse Semiconductor Corp, vsc8124 Datasheet - Page 3

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vsc8124

Manufacturer Part Number
vsc8124
Description
2.488 Gb/s Quad Data Re-timer
Manufacturer
Vitesse Semiconductor Corp
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
vsc8124RE
Manufacturer:
AMCC
Quantity:
1 831
VSC8124
2/23/00
Target Specification
G52271-0, Rev. 1.14
Functional Description
Reference Clock
ence clock phase can be tolerated without data error at slightly reduced jitter tolerance. (See Table 1) Phase
changes must not occur more often than every 20 s. Serial data transition density must average
period. Two reference clock input ports are provided. The REFSEL pin selects the active port. When REFSEL
is not driven, it floats low, selecting REFCK0. Changing REFSEL implies a phase change.
Clock Recovery
each channel, a phase detector and low pass filter force a local clock to track the average phase of the incoming
serial data. The low pass filter is first order to prevent jitter peaking in cascaded devices.
Table 1: Serial Input Data Specification
NOTE: 1) Jitter tolerance is measured at worst case power supply and temperature, using 155.52 MHz clean reference clock
Parameter
A clean reference clock should be provided to meet jitter specifications. An arbitrary discontinuity in refer-
The incoming serial data on each channel is presented to a clock recovery and data re-timing circuit. For
Period
2) Jitter tolerance and re-timed data jitter are degraded in FASTLOCK mode.
3) Reference clock frequency tolerance: f
4) Jitter tolerance specifications do not apply in re-timer bypass mode.
J
J
J
(REFCK to meet 2.0 ps RMS jitter at less than 10 Mhz in bandwidth), and 600mV swing differential PRBS data
with150ps maximum rise time.
T
T
T
Jitter tolerance
Jitter tolerance
Jitter tolerance
Description
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
J
T
VITESSE
Figure 1: Serial Input Data Eye Diagram
SEMICONDUCTOR CORPORATION
VITESSE SEMICONDUCTOR CORPORATION
Min
220
150
190
-
100 ppm
Eye Opening
Period
401.88
Typ
170
210
-
Max
-
-
-
-
Units
ps
ps
ps
ps
Within 20
REFCLK phase
Normal Operation
2.488 Gb/s Quad
Fast Lock Mode
Conditions
Data Re-timer
change
0.5
s after
for that
Page 3

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