vsc8122 Vitesse Semiconductor Corp, vsc8122 Datasheet - Page 5

• Manufacturer Part Number: vsc8122
• Description: Multi-rate Sonet/sdh Clock And Data Recovery Ic
• Manufacturer: Vitesse Semiconductor Corp

VSC8122
G52228-0, Rev 4.1
01/05/01
Data Sheet
Table 2: Reference Frequency
Loop Filter
differential, therefore the loop filter must also be fully differential. One capacitor should be connected between
FILTAO and FILTAI, with the other connected between FILTAON and FILTAIN. Recommended capacitors are
low-inductance 1.0 µ F (0603 or 0805) ceramic SMT X7R devices, 6.3 WVDC or greater, with tolerance of 10%
or better.
AC Characteristics
Table 3: AC Characteristics
t
t
t
Jitter
Jitter
LBW
Jitter
pd
r
r
,t
,t
Parameters
f
f
The Phase-Lock Loop (PLL) on the VSC8122 employs two external capacitors. The PLL design is fully
gen
tol
peak
155.52MHz (156.25MHz)
Center of output data eye from
rising edge of CO+
DO± rise and fall times
CO± rise and fall times
Jitter Generation (12kHz-
20MHz)
Jitter Tolerance
Loop Bandwidth
Jitter Peaking
Reference Frequency
19.44MHz (19.53MHz)
38.88MHz (39.06MHz)
77.76MHz (78.13MHz)
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Description
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
(Over recommended operating conditions)
VITESSE
SEMICONDUCTOR CORPORATION
Min
-75
—
—
—
—
—
—
Internet: www.vitesse.com
Typ
—
—
—
—
—
—
—
REF_SEL0
Max
+75
150
135
3.6
2.0
0.1
—
0
1
0
1
ps - rms
Units
MHz
dB
—
ps
ps
ps
20% to 80% into 50Ω load.
20% to 80% into 50Ω load.
Measured at the HS data output for
jitter in the 12kHz - 20MHz band.
Assume 1.2ps rms input data jitter.
Exceeds SONET/SDH mask
-3dB point of jitter transfer curve
Clock and Data Recovery IC
Multi-Rate SONET/SDH
Conditions
REF_SEL1
0
0
1
1
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