lmx2515 National Semiconductor Corporation, lmx2515 Datasheet - Page 10

• Manufacturer Part Number: lmx2515
• Description: Pllatinum? Frequency Synthesizer System With Integrated Vco
• Manufacturer: National Semiconductor Corporation

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Functional Description
VCO SELECTION
The RF_SEL bit must be used to select the RF VCO output.
When using the LMX2515LQ0701 the RF_SEL bit must be
set to "0". When using the LMX2515LQ1321 the RF_SEL bit
must be set to "1".
Note 13: LD output becomes low when the phase error is larger than t
Note 14: LD output becomes high when the phase error is less than t
four or more consecutive cycles.
Note 15: Phase Error is measured on leading edge. Only errors greater than
t
W1
and t
CE pin
HIGH
HIGH
W2
LOW
LOW
RF_SEL Bit
are labeled.
TABLE 1. Power Down Modes
0
1
TABLE 2. VCO Selection
FIGURE 2. Lock Detect Timing Diagram Waveform (Notes 13, 14, 15, 16, 17)
RF_PD Bit
0
1
0
1
LMX2515LQ0701
LMX2515LQ1321
(Continued)
Mode
Not Active
Not Active
Not Active
Mode
Active
W1
W2
for
.
10
LOCK DETECT MODE
The LD output can be used to indicate the lock status of the
PLL. Bit 6 in Register R1 determines the signal that appears
on the LD pin. When the PLL is not locked, the LD pin
remains LOW. After obtaining phase lock, the LD pin will
have a logical HIGH level. The LD output is always low when
the LD register bit is 0 and in power down mode.
Note 16: t
t
Note 17: The lock detect comparison occurs with every 64
f
W2
N
is 10 ns for both devices.
RF-PLL Section
W1
Not Locked
Locked
LD Bit
is 5 ns for LMX2515LQ1321 and 10 ns for LMX2515LQ0701.
TABLE 3. Lock Detect Modes
0
1
TABLE 4. Lock Detect Logic
Disable (GND)
LD Output
Enable
Mode
HIGH
LOW
20068808
th
cycle of f
R
and