lmx2532 National Semiconductor Corporation, lmx2532 Datasheet - Page 8

• Manufacturer Part Number: lmx2532
• Description: Pllatinum Frequency Synthesizer System With Integrated Vcos
• Manufacturer: National Semiconductor Corporation

www.national.com
Functional Description
VCO FREQUENCY TUNING
The center frequency of the RF VCO is mainly determined
by the resonant frequency of the tank circuit. This tank circuit
is implemented on-chip and requires no external inductor.
The LMX2522/32 actively tunes the tank circuit to the re-
quired frequency with the built-in tracking algorithm.
BANDWIDTH CONTROL AND FREQUENCY LOCK
During the frequency acquisition period, the loop bandwidth
is significantly extended to achieve frequency lock. Once
frequency lock occurs, the PLL will return to a steady state
condition with the loop bandwidth set to its nominal value.
The transition between acquisition and lock modes occurs
seamlessly and extremely fast, thereby, meeting the strin-
gent requirements associated with lock time and phase
noise. Several controls (BW_DUR, BW_CRL and BW_EN)
are used to optimize the lock time performance.
SPURIOUS REDUCTION
To improve the spurious performance of the device one of
two types of spurious reduction schemes can be selected:
The spurious reduction can also be disabled, but it is recom-
mended that the continuous optimization mode be used for
normal operation.
Note 9: LD output becomes low when the phase error is larger than t
Note 10: LD output becomes high when the phase error is less than t
four or more consecutive cycles.
Note 11: Phase Error is measured on leading edge. Only errors greater than
t
• A continuous optimization scheme, which tracks the en-
• A one time optimization scheme, which sets the internal
W1
LMX2522LQ1635
LMX2532LQ0967
LMX2532LQ1065
vironmental and voltage variations, giving the best spuri-
ous performance over changing conditions
compensation values only when the PLL goes into a
locked state.
and t
Device Type
W2
are labeled.
TABLE 4. IF Frequencies
440.76
170.67
367.20
(MHz)
f
VCO
IF_B
229
191
88
FIGURE 1. Lock Detect Timing Diagram Waveform
IF_A
(Continued)
15
9
4
f
OSC
(kHz)
120
120
120
/IF_R
W1
W2
.
for
8
POWER DOWN MODE
The LMX2522 and LMX2532 include a power down mode to
reduce the power consumption. The LMX2522/32 enters into
the power down mode either by taking the CE pin LOW or by
setting the power down bits in Register R1. Table 5 summa-
rizes the power down function. If CE is set LOW, the circuit is
powered down regardless of the register values. When CE is
HIGH, the IF and RF circuitry are individually powered down
by setting the register bits.
X = Don’t care.
LOCK DETECT
The LD output can be used to indicate the lock status of the
RF PLL. Bit 21 in Register R0 determines the signal that
appears on the LD pin. When the RF PLL is not locked, the
LD pin remains LOW. After obtaining phase lock, the LD pin
will have a logical HIGH level. The output can also be
programmed to be ground at all times.
Note 12: t
Note 13: The lock detect comparison occurs with every 64
f
N
CE Pin
.
0
1
1
1
1
RF PLL Section
W1
LD Bit
TABLE 5. Power Down Configuration
Not Locked
and t
RF_EN
TABLE 7. Lock Detect Logic Table
0
1
Locked
TABLE 6. Lock Detect Modes
X
0
0
1
1
W2
are equal to 10 ns.
IF_EN
X
0
1
0
1
RF Circuitry
OFF
OFF
OFF
ON
ON
Disable (GND)
Enable
Mode
LD Output
HIGH
LOW
20067205
IF Circuitry
th
cycle of f
OFF
OFF
OFF
ON
ON
R
and