sy89826l Micrel Semiconductor, sy89826l Datasheet - Page 2

• Manufacturer Part Number: sy89826l
• Description: Sy89826l 3.3v 1ghz Precision 1 22 Lvds Fanout Buffer/translator With 2 1 Input Mux
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
M9999-011907
[e-mail] or [phone]
63, 61, 59, 57, 55, 53,
62, 60, 58, 56, 54, 52,
36, 34, 30, 28, 26, 24,
51, 47, 45, 43, 41, 39,
50, 46, 44, 42, 40, 38,
/LVPECL_CLK
37, 35, 31, 29, 27, 25,
LVPECL_CLK
PACKAGE/ORDERING INFORMATION
PIN DESCRIPTIONS
/LVDS_CLK
LVDS_CLK
CLK_SEL
23, 21, 19, 15
22, 20, 18, 14
Pin Number
GNDO
GNDO
2, 13, 33, 48
VCCO
VCCO
GNDI
VCCI
/Q21
Q21
32, 49, 64
1, 16, 17,
NC
OE
NC
3, 12
5, 6
8, 9
11
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64-Pin TQFP (H64-1)
7
4
64
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
/LVPECL_CLK
LVPECL_CLK
/LVDS_CLK
LVDS_CLK
/Q0 – /Q21
Pin Name
CLK_SEL
Q0 – Q21
GNDO
VCCO
GNDI
VCCI
OE
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GNDO
Q7
/Q7
Q8
/Q8
Q9
/Q9
Q10
/Q10
Q11
/Q11
Q12
/Q12
Q13
/Q13
GNDO
Output
Output
Power
Power
Power
Power
Input
Input
Input
Input
I/O
Ordering Information
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
Part Number
SY89826LHI
SY89826LHITR
SY89826LHY
SY89826LHYTR
terminator
LVPECL
w/100
internal (Figure 2) includes internal termination, and is intended to interface
LVTTL/
LVTTL/
CMOS
LVDS
LVDS
LVDS
Type
Pull-down Pin Function
pull-down HIGH (Can be left floating if CLKSEL = LOW). Requires
(Figure 1) external termination. Leave floating if not used.
Internal
11k to
Pull-up/
pull-up
3.3k
(3)
75k
VCCI
(2)
2
(2, 3)
Package
Differential LVDS clock input. Selected when CLKSEL = LOW
(Can be left floating if CLKSEL = HIGH). This input pair
directly to LVDS. Leave floating if not used.
Differential LVPECL clock input. Selected when CLKSEL =
Selects LVDS_CLK when LOW and LVPECL_CLK when
HIGH. Default condition is HIGH if left floating.
Output enable/disable function. When LOW, Q outputs go
LOW, /Q outputs go HIGH. Asynchronous input that is
synchronized internally to prevent output glitches or runt
pulses.
Differential LVDS clock outputs when OE = HIGH and static
LOW when OE = LOW. Unused output pairs must be
terminated with 100 across the differential pair to maintain
low skew and jitter.
Differential clock outputs (complement) when OE = HIGH
and static HIGH when OE = LOW. Unused output pairs
must be terminated with 100 across the differential pair to
maintain low skew and jitter.
Core VCC connect to 3.3V supply. Not connected to
VCCO internally. Connect to VCCO on PCB. Bypass
with 0.1 F in parallel with 0.01 F low ESR capacitors as
close to VCC pins as possible.
Output buffer VCC connects to 3.3V supply. Not connected
to VCCI internally. Connect to VCCI on PCB. Bypass
with 0.1 F in parallel with 0.01 F low ESR capacitors as
close to VCC pins as possible.
Core ground not connected to GNDO internally.
Connect to GNDO on PCB.
Output buffer ground not connected to GNDI internally.
Connect to GNDI on PCB.
No connect pins to be left open.
H64-1
H64-1
H64-1
H64-1
Type
(1)
Operating
Industrial
Industrial
Industrial
Industrial
Range
Pb-Free bar-line indicator Matte-Sn
Pb-Free bar-line indicator Matte-Sn
SY89826LHY with
SY89826LHY with
A
SY89826LHI
SY89826LHI
= 25 C, DC electricals only.
Package
Marking
Precision Edge
SY89826L
Pb-Free
Pb-Free
Finish
Sn-Pb
Sn-Pb
Lead
®