ics650-12 Integrated Device Technology, ics650-12 Datasheet - Page 5

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ics650-12

Manufacturer Part Number
ics650-12
Description
Mpeg Clock Synthesizer
Manufacturer
Integrated Device Technology
Datasheet
AC Electrical Characteristics
External Components
IDT™ / ICS™ MPEG CLOCK SYNTHESIZER
Input Crystal or Clock Frequency
Output Clocks Accuracy (synthesis error)
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
One Sigma Jitter, ACLK
Absolute Clock Period Jitter
ICS650-12
MPEG CLOCK SYNTHESIZER
Unless stated otherwise, VDD = 3.3 V or 5 V, Ambient Temperature 0 to +70 C
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF
should be connected between VDD and GND on pins 4 and 6, 16 and 14, and a 33 terminating resistor may be
used on each clock output if the trace is longer than 1 inch.
Parameter
Symbol
t
t
OR
OF
All clocks
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
VDD = 3.3 V
VDD = 5.0 V
VDD = 3.3 V, except
CCLK = 20 MHz
VDD = 5.0 V, except
CCLK = 20 MHz
5
Conditions
Min.
40
±300
±200
Typ. Max. Units
100
50
27
40
0
ICS650-12
CLOCK SYNTHESIZER
1.5
1.5
60
1
MHz
ppm
ns
ns
ps
ps
ps
ps
%
REV D 102709

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