ics9p935 Integrated Device Technology, ics9p935 Datasheet - Page 8

• Manufacturer Part Number: ics9p935
• Description: Ddr I/ddr Ii Phase Lock Loop Zero Delay Buffer
• Manufacturer: Integrated Device Technology

Timing Requirements
Switching Characteristics
Notes:
1.
2.
3.
4.
IDT
T
Max clock frequency
Application Frequency
Range
Input clock duty cycle
CLK stabilization
Low-to high level
propagation delay time
High-to low level propagation
delay time
Period jitter
Half-period jitter
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter
Static Phase Offset
Output to Output Skew
A
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
TM
= 0 - =70°C; Supply Voltage A
Refers to transition on noninverting output in PLL bypass mode.
While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=t
decreases as the frequency goes up.
Switching characteristics guaranteed for application frequency range.
Static phase offset shifted by design.
/ICS
PARAMETER
PARAMETER
TM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
1
t
(static phase offset)
3
SYMBOL
SYMBOL
t(jit_hper)
VDD
T
freq
freq
T
T
cyc
T
t
t
d
t
STAB
jit (per)
PLH
t
, V
PLL
sl(o)
skew
sl(i)
tin
-T
App
op
1
1
DD
cyc
= 2.5 V +/- 0.2V (unless otherwise stated)
4
2.5V+0.2V @ 25
2.5V+0.2V @ 25
BUF_IN to any output
BUF_IN to any output
100MHz to 200MHz
100MHz to 200MHz
100MHz to 200MHz
CONDITIONS
CONDITION
8
wH
/t
o
o
c
C
C
, were the cycle (t
MIN
45
95
40
MIN
-100
-30
-50
-50
1
1
c
)
MAX
600
233
60
15
TYP
3.5
3.5
0
UNITS
MHz
MHz
ICS9P935
µs
%
MAX
100
30
50
50
40
4
2
UNITS
V/ns
V/ns
REV H 12/1/08
ns
ns
ps
ps
ps
ps
ps