ics83940dyi-01t Integrated Device Technology, ics83940dyi-01t Datasheet - Page 10
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ics83940dyi-01t
Manufacturer Part Number
ics83940dyi-01t
Description
Lvpecl/lvcmos-input Lvcmos-output 1 18 250-mhz Clock Buffer
Manufacturer
Integrated Device Technology
Datasheet
1.ICS83940DYI-01T.pdf
(15 pages)
IDT™ / ICS™ LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
ICS83940-01
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
LVPECL C
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
and V
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
F
83940DY-01
F
F
IGURE
IGURE
IGURE
CMR
2A. H
2C. H
2E. H
3.3V
3.3V
input requirements. Figures 2A to 2E show inter-
2.5V
LVPECL
CML
BY AN
BY AN
BY A
SSTL
LOCK
I
I
I
P
P
P
Integrated
Circuit
Systems, Inc.
ER
ER
ER
3.3V LVPECL D
O
SSTL D
C
C
Zo = 50 Ohm
Zo = 50 Ohm
C
I
Zo = 50 Ohm
Zo = 50 Ohm
PEN
LOCK
LOCK
LOCK
Zo = 60 Ohm
Zo = 60 Ohm
NPUT
C
S PCLK/nPCLK I
S PCLK/nPCLK I
S PCLK/nPCLK I
OLLECTOR
SWING
RIVER
I
NTERFACE
3.3V
R1
50
2.5V
R3
120
and V
3.3V
R3
125
R1
120
R1
84
RIVER
R2
50
CML D
R4
120
R2
120
R4
125
OH
R2
84
PCLK
nPCLK
must meet the V
3.3V
www.icst.com/products/hiperclocks.html
PCLK
nPCLK
RIVER
PCLK
nPCLK
3.3V
NPUT
NPUT
NPUT
HiPerClockS
PCLK/nPCLK
3.3V
HiPerClockS
PCLK/nPCLK
Input
D
D
D
HiPerClockS
RIVEN
RIVEN
RIVEN
LVPECL-
PP
10
10
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
F
F
F
IGURE
IGURE
IGURE
3.3V
3.3V
TO
3.3V
2B. H
3.3V LVPECL
2D. H
2F. H
LVDS
-LVCMOS / LVTTL F
CML Built-In Pullup
R5
100 - 200
BY A
BY A
BY A
I
I
Zo = 50 Ohm
Zo = 50 Ohm
I
P
P
P
ER
ER
ER
B
3.3V LVPECL D
3.3V LVDS D
R6
100 - 200
C
UILT
C
C
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
LOCK
LOCK
-I
R5
100
N
S PCLK/nPCLK I
S PCLK/nPCLK I
S PCLK/nPCLK I
Zo = 50 Ohm
Zo = 50 Ohm
P
ULLUP
C1
C2
L
RIVER
C1
C2
CML D
OW
3.3V
R3
84
RIVER WITH
R1
125
R1
100
3.3V
R3
1K
R1
1K
S
R4
84
ANOUT
R2
125
RIVER
KEW
REV. A NOVEMBER 18, 2005
R4
1K
PCLK
nPCLK
R2
1K
3.3V
NPUT
NPUT
NPUT
AC C
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
PCLK
nPCLK
, 1-
3.3V
3.3V
D
D
D
B
RIVEN
RIVEN
HiPerClockS
PCL K/n PC LK
RIVEN
OUPLE
HiPerClockS
PCLK/nPCLK
TO
UFFER
ICS83940-01
-18
TSD