ics83940dyi-01t Integrated Device Technology, ics83940dyi-01t Datasheet

no-image

ics83940dyi-01t

Manufacturer Part Number
ics83940dyi-01t
Description
Lvpecl/lvcmos-input Lvcmos-output 1 18 250-mhz Clock Buffer
Manufacturer
Integrated Device Technology
Datasheet
IDT™ / ICS™ LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL
FANOUT BUFFER
G
pair can accept LVPECL, CML or SSTL input levels. The single
ended clock input accepts LVCMOS or LVTTL input levels.
The low impedance LVCMOS/LVTTL outputs are designed
to drive 50Ω series or parallel terminated transmission lines.
The effective fanout can be increased from 18 to 36 by
utilizing the ability of the outputs to drive two series termi-
nated lines.
The ICS83940-01 is characterized at full 3.3V, full 2.5V
and mixed 3.3V input and 2.5V output operating supply
modes. Guaranteed output and part-to-part skew charac-
teristics make the ICS83940-01 ideal for those clock distri-
bution applications demanding well defined performance
and repeatability.
83940DY-01
B
HiPerClockS™
IC S
LVCMOS_CLK
ENERAL
LOCK
CLK_SEL
nPCLK
PCLK
The ICS83940-01 is a low skew, 1-to-18 LVPECL-
to-LVCMOS/LVTTL Fanout Buffer and a member
of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS83940-01 has
two selectable clock inputs. The PCLK, nPCLK
D
IAGRAM
Integrated
Circuit
Systems, Inc.
D
ESCRIPTION
0
1
www.icst.com/products/hiperclocks.html
18
Q0:Q17
LVPECL-
1
1
P
F
• Eighteen LVCMOS/LVTTL outputs, 23Ω typical output
• Selectable LVCMOS_CLK or LVPECL clock inputs
• LVCMOS_CLK supports the following input types:
• PCLK, nPCLK supports the following input types:
• Maximum output frequency: 250MHz
• Output skew: 85ps (maximum)
• Part-to-part skew: 750ps (maximum)
• Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
impedance
LVCMOS or LVTTL
LVPECL, CML, SSTL
packages
IN
EATURES
LVCMOS_CLK
TO
A
CLK_SEL
-LVCMOS / LVTTL F
SSIGNMENT
nPCLK
PCLK
GND
GND
V
V
DDO
DD
7mm x 7mm x 1.4mm package body
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
ICS83940-01
32-Lead LQFP
Y Pacakge
Top View
L
ICS83940-01
OW
S
ANOUT
KEW
REV. A NOVEMBER 18, 2005
DATA SHEET
ICS83940-01
24
23
22
21
20
19
18
17
, 1-
B
Q6
Q7
Q8
V
Q9
Q10
Q11
GND
TO
UFFER
DDO
-18
ICS83940-01

Related parts for ics83940dyi-01t

ics83940dyi-01t Summary of contents

Page 1

Integrated LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL Circuit FANOUT BUFFER Systems, Inc ENERAL ESCRIPTION The ICS83940- low skew, 1-to-18 LVPECL to-LVCMOS/LVTTL Fanout Buffer and a member HiPerClockS™ of the HiPerClockS™ family of High Performance Clock Solutions ...

Page 2

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc ABLE IN ESCRIPTIONS ...

Page 3

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Input Current Storage Temperature, T STG T 4A ...

Page 4

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc ABLE HARACTERISTICS ...

Page 5

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc ABLE HARACTERISTICS ...

Page 6

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc ABLE HARACTERISTICS ...

Page 7

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc. P ARAMETER 1.65V±5% V DD, V DDO LVCMOS GND -1.65V±5% 3. UTPUT OAD EST IRCUIT 1.25V±5% V DD, V DDO LVCMOS GND -1.25V±5% 2.5V ...

Page 8

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc. 80% 20% Clock t Outputs UTPUT ISE ALL IME V DDO 2 LVCMOS_CLK nPCLK PCLK Q0:Q17 ROPAGATION ELAY 83940DY-01 IDT™ ...

Page 9

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V ...

Page 10

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc. LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V SWING and V input requirements. Figures ...

Page 11

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc. θ ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern ...

Page 12

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc ACKAGE UTLINE UFFIX FOR ABLE ...

Page 13

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc ABLE RDERING NFORMATION ...

Page 14

Integrated ICS83940-01 Circuit LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Systems, Inc 83940DY-01 IDT™ / ICS™ LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL ...

Page 15

... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners ...

Related keywords