ics8745b Integrated Device Technology, ics8745b Datasheet - Page 2

• Manufacturer Part Number: ics8745b
• Description: 1 5 Differential-to-lvds Zero Delay Clock Generator
• Manufacturer: Integrated Device Technology

Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR
Symbol
C
R
R
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
13, 19, 25
16, 22, 28
IN
PULLUP
PULLDOWN
Number
12, 29
14, 15
17, 18
20, 21
23, 24
26, 27
9, 32
1, 2,
10
11
30
31
3
4
5
6
7
8
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
SEL0, SEL1,
SEL2 SEL3
CLK_SEL
PLL_SEL
Q0/Q0
Q1/Q1
Q2/Q2
Q3/Q3
Q4/Q4
Name
CLK0
CLK0
CLK1
CLK1
V
V
FBIN
FBIN
GND
V
MR
DDO
DDA
DD
Output
Output
Output
Output
Output
Power
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pullup
Test Conditions
Description
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Clock select input. When HIGH, selects CLK1, CLK1.
When LOW, selects CLK0, CLK0. LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs Qx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Core supply pins.
Inverting differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.”
Power supply ground.
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Analog supply pin.
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock.
LVCMOS/LVTTL interface levels.
2
Minimum
ICS8745BYREV. C OCTOBER 27, 2008
Typical
51
51
4
Maximum
Units
k
k
pF
Ω
Ω