ics87952-147 Integrated Device Technology, ics87952-147 Datasheet - Page 8

• Manufacturer Part Number: ics87952-147
• Description: High-fanout Lvcmos-input Lvcmos-output 1 11 180-mhz Clock Generator
• Manufacturer: Integrated Device Technology

The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
C
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
87952AYI-147
OWER AND
LOCK
T
RACES AND
G
DDA
Integrated
Circuit
Systems, Inc.
ROUNDING
pin as possible.
T
ERMINATION
U1
VCCA
R7
Pin 1
C6
C16
F
IGURE
50 Ohm
Trace
C11
LVCMOS / LVTTL C
www.icst.com/products/hiperclocks.html
2B. PCB B
R1
C1
OARD
R2
L
50 Ohm
Trace
8
AYOUT
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
• The 50Ω output traces should have same length.
• Avoid sharp angles on the clock trace. Sharp angle
• Keep the clock traces on the same layer. Whenever pos-
• To prevent cross talk, avoid routing other signal traces in
• The series termination resistors should be located as
turns cause the characteristic impedance to change on
the transmission lines.
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
close to the driver pins as possible.
F
C5
C2
OR
LOCK
ICS87952I-147
C4
C3
M
ULTIPLIER
ICS87952I-147
Other
signals
GND
VDD
VIA
/Z
L
OW
ERO
S
D
KEW
ELAY
REV. B APRIL 10, 2006
, 1-
B
TO
UFFER
-11