ics87952-147 Integrated Device Technology, ics87952-147 Datasheet - Page 7

• Manufacturer Part Number: ics87952-147
• Description: High-fanout Lvcmos-input Lvcmos-output 1 11 180-mhz Clock Generator
• Manufacturer: Integrated Device Technology

87952AYI-147
L
The schematic of the ICS87952I-147 layout example is shown
in Figure 2A. This layout example is used as a general guide-
line. The layout in the actual system will depend on the se-
AYOUT
Logic Input Pin Examples
VDD
VDD
RU1
1K
RD1
Not Install
G
Driv er_LVCMOS
F
Q1
Set Logic
Input to
'1'
IGURE
UIDELINE
To Logic
Input
pins
Ro ~ 7 Ohm
Integrated
Circuit
Systems, Inc.
2A. ICS87952I-147 LVCMOS/LVTTL C
R3
VDD
43
RU2
Not Install
RD2
1K
Set Logic
Input to
'0'
To Logic
Input
pins
Zo = 50
VDD
LVCMOS / LVTTL C
www.icst.com/products/hiperclocks.html
F_SELC
F_SELB
F_SELA
10 - 15
10u
R7
C16
VDD
R4
1K
0.01u
C11
ICS87952I-147
ICS87952
1
2
3
4
5
6
7
8
U1
VCO_SEL
F_SELC
F_SELB
F_SELA
MR/nOE
REF_CLK
GNDI
FB_IN
R5
1K
LOCK
7
lected component types, the density of the components, the
density of the traces, and the stack up of the P.C. board.
M
ULTIPLIER
0.1u
C1
(U1-16)
LOCK
GNDO
GNDO
VDDO
VDDO
VDD=3.3V
0.1uF
/Z
C2
QB1
QB0
QA4
QA3
ERO
VDDO
VDD
M
R1
24
23
22
21
20
19
18
17
D
ULTIPLIER
ELAY
43
R2
(U1-20)
B
43
UFFER
ICS87952I-147
Zo = 50
0.1uF
C3
/Z
S
L
Zo = 50
(U1-21)
CHEMATIC
OW
ERO
0.1uF
C4
S
D
(U1-25)
KEW
E
ELAY
XAMPLE
Receiv er
REV. B APRIL 10, 2006
Receiv er
0.1uF
C5
, 1-
B
(U1-32)
TO
UFFER
-11
0.1uF
C6