ics87951 Integrated Device Technology, ics87951 Datasheet - Page 8

• Manufacturer Part Number: ics87951
• Description: Differential Or Lvcmos-input Lvcmos-output 2 9 180-mhz Clock Generator
• Manufacturer: Integrated Device Technology

W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
P
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87951I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V
87951AYI
OWER
IRING THE
S
UPPLY
D
Integrated
Circuit
Systems, Inc.
IFFERENTIAL
F
ILTERING
T
I
F
NPUT TO
ECHNIQUES
IGURE
Single Ended Clock Input
1. S
DDA
A
A
www.icst.com/products/hiperclocks.html
pin.
PPLICATION
D
CCEPT
INGLE
IFFERENTIAL
DDA
E
and V
S
NDED
C1
0.1u
INGLE
V_REF
DD
/2 is
S
DDO
IGNAL
E
8
-
I
NDED
TO
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
NFORMATION
D
1K
-LVCMOS/LVTTL Z
R1
1K
R2
RIVING
VDD
L
EVELS
D
CLK
nCLK
F
IFFERENTIAL
IGURE
2. P
V
V
DDA
DD
I
NPUT
OWER
DD
.01μF
= 3.3V, V_REF should be 1.25V
.01μF
S
UPPLY
ERO
L
3.3V
OW
ICS87951I
10Ω
10μF
F
D
ILTERING
S
REV. B NOVEMBER 23, 2005
ELAY
KEW
, 1-
B
UFFER
TO
-9