ics87951 Integrated Device Technology, ics87951 Datasheet

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ics87951

Manufacturer Part Number
ics87951
Description
Differential Or Lvcmos-input Lvcmos-output 2 9 180-mhz Clock Generator
Manufacturer
Integrated Device Technology
Datasheet

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G
single ended clock input accepts LVCMOS or LVTTL input
levels. The CLK1, nCLK1 pair can accept most standard differ-
ential input levels. With output frequencies up to 180MHz, the
ICS87951I is targeted for high performance clock applications.
Along with a fully integrated PLL, the ICS87951I contains fre-
quency configurable outputs and an external feedback input for
regenerating clocks with “zero delay”.
87951AYI
P
HiPerClockS™
IC S
ENERAL
IN
DIV_SELC
DIV_SELD
DIV_SELA
DIV_SELB
A
EXT_FB
CLK1
GND
SSIGNMENT
V
DDA
7mm x 7mm x 1.4mm package body
The ICS87951I is a low voltage, low skew 1-to-9
Differential-to-LVCMOS/LVTTL Cock Generator
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS87951I has two selectable clock inputs. The
Integrated
Circuit
Systems, Inc.
D
1
2
3
4
5
6
7
8
ESCRIPTION
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
32-Lead LQFP
ICS87951I
Y package
Top View
www.icst.com/products/hiperclocks.html
D
24
23
22
21
20
19
18
17
IFFERENTIAL
QC0
V
QC1
GND
QD0
V
QD1
GND
DDO
DDO
1
-
TO
• Fully integrated PLL
• Nine single ended 3.3V LVCMOS/LVTTL outputs
• Selectable single ended CLK0 or differential
• The single ended CLK0 input can accept the following
• CLK1, nCLK1 supports the following input types:
• Output frequency range: 25MHz to 180MHz
• VCO range: 200MHz to 480MHz
• External feedback for ”zero delay” clock regeneration
• Cycle-to-cycle jitter: ±100ps (typical)
• Output skew: 375ps (maximum)
• PLL reference zero delay: 350ps window (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
F
CLK1, nCLK1 inputs
input levels: LVCMOS or LVTTL input levels
LVDS, LVPECL, LVHSTL, SSTL, HCSL
packages
EATURES
-LVCMOS/LVTTL Z
ERO
L
OW
ICS87951I
D
S
REV. B NOVEMBER 23, 2005
ELAY
KEW
, 1-
B
UFFER
TO
-9

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ics87951 Summary of contents

Page 1

... The CLK1, nCLK1 pair can accept most standard differ- ential input levels. With output frequencies up to 180MHz, the ICS87951I is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS87951I contains fre- quency configurable outputs and an external feedback input for regenerating clocks with “zero delay”. ...

Page 2

... EXT_FB Internal Pulldown DIV_SELB Internal Pulldown DIV_SELC Internal Pulldown MR/nOE Internal Pulldown DIV_SELD 87951AYI D - -LVCMOS/LVTTL Z IFFERENTIAL PHASE VCO DETECTOR 200-480MHz LPF POWER-ON RESET www.icst.com/products/hiperclocks.html 2 ICS87951I KEW D ERO ELAY ÷ ÷ ÷ QC0 0 1 QC1 QD0 ...

Page 3

... www.icst.com/products/hiperclocks.html 3 ICS87951I KEW D ERO ELAY ...

Page 4

... www.icst.com/products/hiperclocks.html 4 ICS87951I KEW D ERO ELAY ...

Page 5

... www.icst.com/products/hiperclocks.html 5 ICS87951I KEW D ERO ELAY = -40°C 85° ...

Page 6

... www.icst.com/products/hiperclocks.html 6 ICS87951I KEW D ERO ELAY = -40°C 85° ...

Page 7

... O S UTPUT nCLK1 2V CLK0, CLK1 0. EXT_FB V DDO (where t(Ø) is any random sample, and t(Ø the sampled cycles measured on controlled edges HASE ITTER AND www.icst.com/products/hiperclocks.html 7 ICS87951I KEW D ERO ELAY I NFORMATION V Cross Points NPUT EVEL V DDO 2 V DDO ...

Page 8

... UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87951I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin ...

Page 9

... D F 3D. H NPUT RIVEN BY IGURE NPUT AND UTPUT INS O : UTPUTS LVCMOS O All unused LVCMOS output can be left floating. We recommend that there is no trace attached. www.icst.com/products/hiperclocks.html 9 ICS87951I KEW D ERO ELAY 3. Ohm CLK Ohm nCLK HiPerClockS Input ...

Page 10

... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS87951I is: 2674 Pin compatible with the MPC951 87951AYI D - -LVCMOS/LVTTL Z IFFERENTIAL ...

Page 11

... ° www.icst.com/products/hiperclocks.html 11 ICS87951I KEW D ERO ELAY ...

Page 12

... L " " " www.icst.com/products/hiperclocks.html 12 ICS87951I ERO ELAY ...

Page 13

... www.icst.com/products/hiperclocks.html 13 ICS87951I KEW D ERO ELAY ...

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