mt46h32m32lfjg-5 Micron Semiconductor Products, mt46h32m32lfjg-5 Datasheet

mt46h32m32lfjg-5

Manufacturer Part Number

mt46h32m32lfjg-5

Description

168-ball X16, X32 Mobile Lpddr Pop Ti Omap Mobile Ddr Sdram Addendum

Manufacturer

Micron Semiconductor Products

Datasheet

1.MT46H32M32LFJG-5.pdf (12 pages)

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Mobile LPDDR

168-Ball Package-on-Package (PoP) TI OMAP™

MT46HxxxMxxLxJG

Features

• Vdd/Vddq = 1.70–1.95V

• Bidirectional data strobe per byte of data (DQS)

• Internal, pipelined double data rate (DDR)

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

• 4 internal banks for concurrent operation

• Data masks (DM) for masking write data—one mask

• Programmable burst lengths (BL): 2, 4, 8, or 16

• Concurrent auto precharge option is supported

• Auto refresh and self refresh modes

• 1.8V LVCMOS-compatible inputs

• On-chip temperature sensor to control self refresh

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• STATUS READ REGISTER (SRR) supported

• Selectable output drive strength

• Clock stop capability

• 64ms refresh

Table 1:

PDF: 09005aef833508fb/Source: 09005aef83350d72

ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by

Architecture

Configuration

Refresh count

Row addressing

Column addressing

architecture; 2 data accesses per clock cycle

aligned with data for WRITEs

per byte

rate

Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.

Configuration Addressing

32 Meg x 16 x 4 banks

128 Meg x 16

16K (A[13:0])

1K (A[9:0])

168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR

16 Meg x 32 x 4 banks

64 Meg x 32

8K (A[12:0])

1K (A[9:0])

Notes: 1. Contact factory for availability.

Options

• Vdd/Vddq

• Configuration

• Device version

• Plastic “green” package

• Timing – cycle time

• Operating temperature range

– 1.8V/1.8V

– 128 Meg x 16 (32 Meg x 16 x 4

– 64 Meg x 32 (16 Meg x 32 x 4 banks)

– 64 Meg x 16 (16 Meg x 16 x 4 banks)

– 32 Meg x 32 (8 Meg x 32 x 4 banks)

– Single die, standard addressing

– 2-die stack, standard addressing

– 168-ball VFBGA (12mm x 12mm)

– 5ns @ CL = 3

– 5.4ns @ CL = 3

– 6ns @ CL = 3

– Commercial (0° to +70°C)

– Industrial (–40°C to +85°C)

banks)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2. Contact factory for remapped SRR output.

16 Meg x 16 x 4 banks

64 Meg x 16

16K (A[13:0])

1K (A[9:0])

SDRAM Addendum

8 Meg x 32 x 4 banks

32 Meg x 32

8K (A[12:0])

1K (A[9:0])

Marking

Preliminary

128M16

64M32

64M16

32M32

None

-54

-5

-6

‡

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