mt48lc2m32b2 Micron Semiconductor Products, mt48lc2m32b2 Datasheet - Page 35

• Manufacturer Part Number: mt48lc2m32b2
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

Burst Read/Single Write
Figure 25:
Figure 26:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
Note:
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
COMMAND
COMMAND
INTERNAL
INTERNAL
ADDRESS
ADDRESS
CLOCK
CLOCK
For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
CLK
CKE
CLK
CKE
D
DQ
IN
NOP
T0
BANK,
COL n
T0
READ
WRITE
BANK,
COL n
T1
T1
D
NOP
n
IN
T2
T2
NOP
35
D
OUT
n
T3
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n + 1
D
OUT
NOP
n + 1
T4
T4
D
NOP
IN
DON’T CARE
T5
T5
NOP
n + 2
D
NOP
IN
n + 2
D
OUT
DON’T CARE
T6
NOP
D
n + 3
OUT
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Commands