ad7886kp Analog Devices, Inc., ad7886kp Datasheet - Page 5

• Manufacturer Part Number: ad7886kp
• Description: Lc2mos 12-bit, 750 Khz/1 Mhz, Sampling Adc
• Manufacturer: Analog Devices, Inc.

REV. B
TERMINOLOGY
Unipolar Offset Error
The ideal first code transition should occur when the analog
input is 1 LSB above AGND. The deviation of the actual transi-
tion from that point is termed the offset error.
Bipolar Zero Error
The ideal midscale transition (i.e., 0111 1111 1111 to 1000
0000 0000) for the +5 V range should occur when the analog
input is at zero volts. Bipolar zero error is the deviation of the
actual transition from that point.
Gain Error
In the unipolar mode, gain error is measured with respect to the
first and last code transition points. The ideal difference be-
tween these points is FS–2 LSBs. For bipolar applications, the
gain error is measured from the midscale transition to both the
first and last code transitions. The ideal difference in this case is
FS/2–1 LSB. The gain error is defined as the deviation between
the ideal difference, given above, and the measured difference.
For the bipolar case, there are two gain errors; the figure in the
specification page represents the worst case. Ideal FS depends
on the +5REF input; for the 0 V to 5 V input, ideal FS = +5REF
and for the 0 V to 10 V and +5 V ranges, ideal FS = 2 + 5REF.
CONVERTER DETAILS
The AD7886 is a triple-pass flash ADC that uses 15 compara-
tors in a 4-bit flash technique to perform the 12-bit conversion
procedure. Each of the 4096 quantization levels is realized inter-
nally with a precision resistor DAC.
The fifteen comparators first compare the analog input voltage
to the V
four most significant bits and selects 1 out of 16 voltage seg-
ments. The comparators are then switched to 15 subvoltages on
that segment to determine the next four bits and select 1 out of
256 voltage segments. A further switching of the comparators to
another 15 subvoltages produces the complete 12-bit conversion
REF
CONVST
/16 voltages of the resistor array. This determines the
DGND
BUSY
DB5
DB3
DB0
DB7
DB6
DB4
DB2
DB1
V
CS
RD
DD
10
12
13
14
11
1
2
3
4
5
6
7
8
9
(Not to Scale)
TOP VIEW
AD7886
DIP
19
18
16
15
28
27
26
25
24
23
22
20
17
21
DB8
DB9
DB10
DB11
V
AGND
V
SUM
+5REF
V
VIN2
VIN1
AGND
V
SS
REF
SS
DD
PIN CONFIGURATIONS
–5–
result. The 12 bits of data are then stored internally in a three-
state output latch.
REFERENCE INPUT
The AD7886 operates from a 3.5 V reference, which must be
provided at the V
an external amplifier can be used for deriving 3.5 V from stan-
dard 5 V references. Figure 2 shows an example with the AD586
which a is a high performance voltage reference exhibiting
excellent stability performance, 5 ppm/ C max. The external
amplifier serves a second function of force/sensing the V
input. Force/sensing minimizes error contributions from
GND
AD586
+V
DGND
+V
BUSY
IN
DB2
DB0
DB3
DB1
V
V
10 F
OUT
DD
C1
AD707
10
11
Figure 2. Typical Reference Circuitry
5
6
7
8
9
–
+
+5V
0.1 F
REF
–3.5V
C2
12
4
input. Two on-chip resistors for use with
13
3
*ADDITIONAL PINS OMITTED FOR CLARITY
(Not to Scale)
+5REF
14
SUM
V
2
TOP VIEW
AD7886
REF
AGND
PLCC
15
1
TO DAC
28
16
27
17
R1
9k
R2
6.3k
26
18
AD7886*
AD7886
25
24
23
22
20
19
21
AGND
V
SUM
+5REF
V
DB11
V
SS
REF
DD
REF