cy7c1380b-200bzc Cypress Semiconductor Corporation., cy7c1380b-200bzc Datasheet - Page 9

• Manufacturer Part Number: cy7c1380b-200bzc
• Description: 512k X 36/1m X 18 Pipelined Sram
• Manufacturer: Cypress Semiconductor Corporation.

Interleaved Burst Sequence
ZZ Mode Electrical Characteristics
Document #: 38-05267 Rev. *A
I
t
t
DDZZ
ZZS
ZZREC
Address
A
Parameter
First
[1:0]]
00
01
10
11
Address
Second
A
01
00
11
10
[1:0]
Sleep mode stand-
Device operation to
ZZ recovery time
Description
by current
ZZ
Address
Third
A
10
11
00
01
[1:0]
Test Conditions
ZZ > V
ZZ > V
ZZ < 0.2V
Address
Fourth
A
DD
DD
10
01
00
11
[1:0]
– 0.2V
– 0.2V
Linear Burst Sequence
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CEs, ADSP, and ADSC must remain inactive for the duration
of t
Address
ZZREC
A
First
2t
Min.
00
01
10
11
[1:0]
CYC
after the ZZ input returns LOW.
Address
Second
A
01
10
11
00
[1:0]
2t
Max.
20
CYC
Address
Third
A
10
11
00
01
[1:0]
CY7C1380B
CY7C1382B
Page 9 of 34
Unit
mA
Address
ns
ns
Fourth
A
11
00
01
10
[1:0]