s908gr32ag3vfa Freescale Semiconductor, Inc, s908gr32ag3vfa Datasheet - Page 136

• Manufacturer Part Number: s908gr32ag3vfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Input/Output (I/O) Ports
12.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1
to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
DDRA7–DDRA0 — Data Direction Register A Bits
Figure 12-4
When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
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These read/write bits control port A data direction. Reset clears DDRA7–DDRA0, configuring all port
A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
shows the port A I/O logic.
Address:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
DDRA7
$0004
Bit 7
0
Figure 12-3. Data Direction Register A (DDRA)
DDRA6
6
0
RESET
Figure 12-4. Port A I/O Circuit
DDRA5
5
0
Table 12-2
NOTE
DDRA4
DDRAx
PTAx
4
0
summarizes the operation of the port A pins.
DDRA3
3
0
PTAPUEx
DDRA2
2
0
DDRA1
1
0
V
DD
INTERNAL
PULLUP
DEVICE
Freescale Semiconductor
DDRA0
Bit 0
PTAx
0