sg2567fbd28451-ibq ETC-unknow, sg2567fbd28451-ibq Datasheet - Page 28
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sg2567fbd28451-ibq
Manufacturer Part Number
sg2567fbd28451-ibq
Description
Dram Module Ddr2 Sdram 2gbyte 240fbdimm
Manufacturer
ETC-unknow
Datasheet
1.SG2567FBD28451-IBQ.pdf
(30 pages)
AMB Initialization
The FBD initialization process generally follows the top-to-bottom sequence of the state transitions shown in the
the high level AMB Initialization Flow diagram. The host must sequence the AMB devices through the Disable, Cal-
ibrate, (back to Disable), Training, Testing, and Polling states in order to transition the AMBs into the active channel
L0 state. The value in paranthesis in each state bubble indicates the condition/activity of the links during these
states.
AMB Initialization Flow Diagram
Each bit lane is initialized (mostly) independently to support fault tolerance. The transitions in the AMB Initialization
Flow Diagram represent the transitions of the AMB core logic state machine and are taken when the transition
event is detected on the minimum required number of southbound bit lanes. The chain of FBDIMM links connecting
the host to the AMBs must each be initialized to establish the timing for broadcasting data frames in the south-
bound direction and for merging data frames in the northbound direction. The AMBs on the channel are generally
initiaized as a group but because each AMB is individually addressable many alternate initialization sequences
may be employed.
Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
Recalibrate (NOPs)
Channel idled to recali-
brate TX and RX circuits.
Disable (EI)
Channel inactive, the
interface signals are in
low-power electrical idle.
Training (TS0)
Initial bit alignment and
frame alignment training.
Testing (TS1)
Each bit lane is individu-
ally tested.
Polling (TS2)
Communicates channel
capabilities of individual
AMB devices.
Config (TS3)
Communicates channel
width configuration of
AMB devices.
L0 (frames)
Active channel; frames of
information flow between
host and AMB devices.
Power-up
Calibratre (1’s)
Low-latency power sav-
ing condition. (Optional)
L0 (EI)
Low-latency power sav-
ing condition. (Optional)
SG2567FBD28451-IBQ
March 24, 2008
28