mbm29dl324te90tr Meet Spansion Inc., mbm29dl324te90tr Datasheet - Page 50

• Manufacturer Part Number: mbm29dl324te90tr
• Description: 32 M 4 M ? 8/2 M ? 16 Bit Dual Operation Flash Memory
• Manufacturer: Meet Spansion Inc.

50
MBM29DL32XTE/BE
• DQ
DQ
these conditions DQ
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA) .
The OE and WE pins will control the output disable functions as described in “MBM29DL32XTE/BE User Bus
Operations (BYTE = V
OPERATION”.
The DQ
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
DQ
used. If this occurs, reset the device with command sequence.
• DQ
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
be used to determine if the sector erase timer window is still open. If DQ
erase cycle has begun. If DQ
the command has been accepted, the system software should check the status of DQ
each subsequent Sector Erase command. If DQ
have been accepted.
See “Hardware Sequence Flags” in “■ COMMAND DEFINITIONS” : Hardware Sequence Flags.
• DQ
Toggle Bit II
This toggle bit II, along with DQ
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
address of the non-erase suspended sector will indicate a logic “1” at the DQ
DQ
Program operation is in progress. The behavior of these two status bits, along with that of DQ
as follows :
For example, DQ
(DQ
DQ
Furthermore, DQ
mode, DQ
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
Exceeded Timing Limits
5
5
2
6
6
2
” in “■ TIMING DIAGRAM”.
bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
is different from DQ
5
3
2
toggles while DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
2
toggles if this bit is read from an erasing sector.
2
2
and DQ
can also be used to determine which sector is being erased. When the device is in the erase
5
will produce a “1”. This is a failure condition which indicates that the program or erase
IH
6
) ” and “MBM29DL32XTE/BE User Bus Operations (BYTE = V
does not.) See also “Toggle Bit Status” in “■ COMMAND DEFINITIONS” and “DQ
7
2
bit and DQ
6
in that DQ
can be used together to determine if the erase-suspend-read mode is in progress.
3
is low (“0”) the device will accept additional sector erase commands. To insure
6
, can be used to determine whether the devices are in the Embedded Erase
Retired Product DS05-20881-8E_July 20, 2007
6
6
never stops toggling. Once the devices have exceeded timing limits, the
toggles only when the standard program or Erase, or Erase Suspend
80 / 90
3
were high on the second status check, the command may not
2
to toggle during the Embedded Erase Algorithm. If the
3
is high (“1”) the internally controlled
2
bit.
IL
3
) ” in “■ DEVICE BUS
prior to and following
7
, is summarized
3
3
may
2
will
vs.