tsa5518m NXP Semiconductors, tsa5518m Datasheet - Page 6

• Manufacturer Part Number: tsa5518m
• Description: 1.3 Ghz Bidirectional I2c-bus Controlled Synthesizer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Read mode
The read data format is summarised in Table 5. Data can
be read out of the device by setting the R/W bit to logic 1.
After the slave address has been recognized, the device
generates an acknowledge pulse and the status word is
transferred on the SDA line (MSB first). Data is valid on the
SDA line during a HIGH of the SCL clock signal. A second
data byte can be read out of the device if the processor
generates an acknowledge on the SDA line. End of
transmission will occur if no acknowledge from the
processor occurs.The device will then release the data line
to allow the processor to generate a STOP condition.
When the port P6 is used as input, it must be programmed
Table 5 Read data format
Notes
1. See Table 7.
2. POR: Power-on reset flag. (POR = 1 on power-on).
3. FL: in lock flag (FL = 1 when the loop is phase-locked).
4. A2, A1, A0: digital outputs of the 5 level A/D converter (see Table 6). Accuracy is
5. Upon an acknowledge pulse from the controller, the device transfers the status byte again. If no acknowledge pulse
Table 6 A/D converter levels
Accuracy on the switching levels is 0.02V
Table 7 Address selection
1997 Mar 07
1
2, ..
BYTE DESCRIPTION
VOLTAGE APPLIED ON PIN P6
1.3 GHz bidirectional I
synthesizer
VOLTAGE APPLIED ON PIN AS
from the controller is received, data read is terminated.
address
status byte(s)
0.45V
0.3V
0.15V
0.6V
0 to 0.15V
0.9V
0.4 to 0.6V
CC
always valid
0 to 0.1V
CC
CC
CC
to 0.45V
CC
to 0.6V
to 0.3V
to 5.5 V
to V
CC
CC
CC
CC
CC
CC
CC
POR
MSB
1
(2)
2
FL
C-bus controlled
1
A2
(3)
1
0
0
0
0
MA1
CC
0
0
1
1
.
A1
0
1
1
0
0
0
0
MA0
0
1
0
1
A0
0
1
0
1
0
0
0
6
in its high-impedance state. The POR flag (Power-on
reset) is set to logic 1 when V
power-on. It is reset when an end of data is detected by the
device (end of a READ sequence). Control of the loop is
made possible with the in-lock flag FL which indicates
(FL = 1) when the loop is phase-locked. A built-in % level
A/D converter is available on I/O port P6. This converter
can be used to feed AFC information to the controller from
the IF section of the television as illustrated in the typical
application circuit in Fig.2. The relationship between bit
A2, A1 and A0 and the input voltage on port P6 is given in
Table 6.
Address selection
The module address contains programmable address bits
(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 3) in one system by applying a
specific voltage on AS input. The relationship between
MA1 and MA0 and the input voltage on AS input is given
in Table 7.
Frequency lock flag (FL) definition
When the FL flag is logic 1, the maximum frequency
deviation dF from stable frequency can be expressed as:
K
I
K
C1, C2 = loop filter capacitors.
df
CP
VCO
O
= 4
= charge pump current (A)
0
0
=
= oscillator slope (Hz/V)
K
-------------
K
VCO
10
MA1
O
A2
6
(4)
(1)
I
CP
MA0
A1
C1
-------------------- -
C1 C2
(4)
(1)
+
1
2
C2
LSB. MSB is transmitted first.
A0
LSB
CC
with:
1
(4)
goes below 3 V and at
Product specification
ACKNOWLEDGE
LOW from device
TSA5518M
note 5